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ANSYS unveils FinFET-ready platform

Posted: 08 May 2014     Print Version  Bookmark and Share

Keywords:ANSYS  FinFET  3D transistor  IC design 

ANSYS Inc. has announced the 2014 version of RedHawk that the company said delivers greater performance, capacity and coverage, as well as sign-off accuracy to address the challenges faced by the increasing complexity of FinFET-based designs. According to ANSYS, the latest offering is the industry-standard power noise and reliability sign-off platform ready for FinFET-based designs.

To meet the demands of lower power consumption and higher operating performance in today's mobile, computing, consumer and automotive electronics, IC designers are adopting FinFET technology, a 3D transistor architecture in which the elevated channel is wrapped by a gate electrode. While FinFET brings many benefits, these designs experience smaller noise and reliability margins, which require tighter control over analysis accuracy.

To meet sign-off quality, SoC dynamic voltage drop analysis requires a flat modelling framework to accurately predict the current flow inside tightly coupled elements across chip, package and PCB. Due to the global nature of power delivery network, a more traditional hierarchical approach cannot deliver the accuracy needed for sign-off. RedHawk version 2014 offers Distributed Machine Processing (DMP) capabilities that deliver on average three times improvement in memory footprint, enabling the simulation of more than 100 million instances or over two billion nodes, while maintaining flat simulation accuracy. DMP's proprietary architecture takes advantage of the increased processing power and memory capacity available in a private machine cluster to simulate each module within the context of the entire chip, including package and PCB elements.

Along with DMP, this release employs software architecture changes and flow optimizations to deliver two to three times runtime improvements over its previous release, which was already the fastest power integrity solution in the market. The combination of DMP and architecture improvements bring capacity and performance required for today's ultra large designs, especially those fabricated using FinFET technologies, without compromising sign-off accuracy.

With the increasing size of SoC, along with variations in the switching current and parasitic profile across the chip, the connection between SoC and package needs to be as granular as possible to deliver quality sign-off. RedHawk version 2014 introduces RedHawk-CPA, the industry's first integrated chip-package co-simulation and co-analysis solution. This option maps the package to the die layout, through pin-to-pin physical connectivity, seamlessly merging a fully distributed package parasitic network with an on-die power delivery network. By incorporating both chip and package layouts in the same simulation environment, RedHawk-CPA provides immediate feedback on the quality of the package design, as well as the impact of package parasitic on the chip's performance.

FinFET-based designs introduce tighter electromigration (EM) limits and a new class of EM rules, as well as greater thermal impact on EM reliability. RedHawk version 2014 is foundry certified for IR-drop and EM analysis for the latest process technology. It supports advanced EM rules that consider current flow direction, metal topology and via types for both power and signal nets. In addition, this release enables thermal-aware EM analysis by providing chip thermal model (CTM) that accurately captures the thermal distribution that is critical for FinFET devices with greater self-heating issues.





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