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LPDDR4 IP sol'n aimed at mobile, graphics-intensive SoCs

Posted: 25 Apr 2014     Print Version  Bookmark and Share

Keywords:Synopsys  mobile SoC  LPDDR4  LPDDR3  memory controller 

Synopsys Inc. has announced what it flaunts as the industry's first complete LPDDR4 IP solution, which includes Synopsys' DesignWare LPDDR4 multiPHY, Enhanced Universal DDR Memory Controller (uMCTL2) and verification IP (VIP), as well as hardening and signal integrity services. The DesignWare LPDDR4 IP solution supports all key LPDDR4 features, including up to 3200Mb/s performance and features to reduce power consumption, delivering a low-power memory solution for mobile and graphics-intensive SoCs, indicated the company.

The DesignWare LPDDR4 IP solution claims to meet the demands of faster processors, high-resolution displays, HD video and graphics-intensive games in mobile SoC applications. Fast frequency switching matches memory bandwidth to the device workload to optimise performance and power consumption. The DesignWare LPDDR4 IP solution can reduce power consumption per bit transferred by incorporating multiple power-saving features such as low-power modes (including power-down, self-refresh and deep power-down), clock gating and power down of sections of the PHY that are not in use at a given moment. These features can extend the battery life of mobile devices and support consumers' increasing requirements for thin and light devices.

To minimise design risk, the DesignWare LPDDR4 IP solution includes backward compatibility with LPDDR3 and DDR3/4 SDRAMs to simplify the design transition from one SDRAM standard to the next. In addition, the LPDDR4 IP supports a split PHY implementation to permit designers to distribute the IP around the SoC, optimising the interface for area-efficient PoP assembly and offering a low-risk evolutionary path from previous-generation mobile memories. Designers can take advantage of Synopsys' DDR hardening and signal integrity services to harden the LPDDR4 multiPHY and to analyse the signal integrity of the entire system (silicon, package and PCB), easing IP integration and reducing potential risks in the use of advanced manufacturing technologies.

The DesignWare Enhanced Universal DDR Memory Controller IP with support for LPDDR4 is available. The DesignWare LPDDR4 multiPHY IP is scheduled to be available in 3Q14 in 16nm FinFET process technology. Verification IP for LPDDR4 is scheduled for early availability in 3Q14.





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