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Hardened floating-point DSP blocks available in Altera FPGA

Posted: 24 Apr 2014     Print Version  Bookmark and Share

Keywords:Altera  FPGA  floating-point DSP  ARM cortex  fixed-point arithmetic 

Recently, Altera has announced hard-core floating-point DSP blocks in its FPGAs and SoCs (in this context, SoCs refers to FPGAs that also contain hard ARM cortex MCU subsystems). Until now, designers working with FPGAs have been forced to realise their DSP algorithms using fixed-point arithmetic.

Now, there are some advantages to working with fixed-point values, but there are a lot of disadvantages also, the main one being that fixed-point values can represent only a limited range of values, which makes fixed-point arithmetic susceptible to a variety of computational inaccuracies.

Similarly, there are some disadvantages when it comes to working with floating-point values, but there are also a lot of advantages, including the fact that they have a much larger dynamic range than their fixed-point cousins.

When it comes to implementing DSP algorithms in FPGAs, designers typically start working at a high level of abstraction, perhaps using MATLAB or Simulink from MathWorks, and they also typically start working with floating-point values. Translating these floating-point representations into fixed-point equivalents is a non-trivial task that can bring the strongest amongst us to our knees. It can take a huge amount of time to ensure that the fixed-point signal path can handle the algorithms without overflowing the values or introducing artifacts into the data stream.

In order to get around this, FPGA designers sometimes implement floating-point data paths using a combination of hardened fixed-point multipliers and soft programmable fabric. Altera has a very nice implementation called Fused Datapath that uses extra bits in the mantissa to reduce the amount of normalisation and de-normalisation operations that have to be performed. Like any other "soft" floating-point implementation, however, these do consume large amounts of programmable fabric resources, burn a lot of power (relatively speaking), and are limited in performance.

With regard to today's announcement, what the folks at Altera have done is really rather clever. They already have a hardened variable-precision fixed-point DSP block that can support standard-precision (18bit) or high-precision (27bit) modes. They've now added a third mode that supports IEEE 754-complient single-precision floating-point calculations.

Hardened floating-point DSP blocks

It turns out that this capability is already in Altera's high-performance mid-range 20nm Arria 10 FPGAs and SoCs, which are currently shipping (the little scamps at Altera held this nugget of information back until they were ready to announce it). This means Arria 10 FPGAs and SoCs will be able to offer DSP datapaths operating at 400-450MHz providing up to 1.5TFLOPS of single-precision floating-point.

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