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Six trends in high-speed memory technologies

Posted: 11 Apr 2014     Print Version  Bookmark and Share

Keywords:-speed memory  Rambus  DDR4  DDR3  embedded DRAM 

TSMC and Renesas have also used eDRAM in the chips they make for the gaming systems, specifically the Microsoft Xbox and the Nintendo Wii. According to an analysis by Chipworks, these use a conventional form of memory stack with polysilicon wine-glass-shaped capacitors. TSMC uses a cell-under-bit stack where the bitline is above the capacitors, while Renesas relies on a cell-over-bit (COB) structure with the bitline below. Intel also uses a COB stack, but the company builds an MIM capacitor in the metal-dielectric stack using a cavity formed in the lower metal level dielectrics. The part is fabbed in Intel's 9-metal, 22nm process.

Graphics RAM GDDR

GDDR4 and GDDR5 graphics RAM are based on DDR3 memory, which has double the data lines compared to DDR2. GDDR5 adds 8bit wide prefetch buffers to boost the performance, and can be configured to operate in x32 mode or x16 mode, which is detected during device initialisation. GDDR5 handles two 32bit wide data words per write clock but uses two different clock types. A differential command clock (CK) is used as a reference for address and command inputs and this is phase-aligned with the forwarded differential write clock (WCK) that is used as a reference for data reads and writes. This WCK runs at twice the CK frequency. The alignment minimises the latency, GDDR5 memories deliver 176Gb/s compared to 168Gb/s for DDR3, although the initial latency is higher for GDDR5.


Static RAM (SRAM) is the fastest memory technology. With many different structures for the memory cells, from one transistor 1T cell to 5 or 6 (6T), there is a trade-off of speed, power consumption and leakage. SRAM is used as discrete memory chips or as the primary and secondary cache in microprocessor systems. Tertiary on-chip cache can be larger and slower, and so can be a different form of SRAM or embedded DRAM. The 4T cell is the most common for its smaller size, while a t6T cell provides higher speeds and more reliability. Cypress Semiconductor sees SRAM not scaling well from 28-16nm to smaller cell size and higher speeds, plateauing out at 1.5GHz, with the best SRAM bitcell size at about 0.09um2. TSMC has reported a bitcell of 0.07um2 at 16nm at IEDM 2013, while at ISSCC2014, Samsung has shown results for a 14nm FinFet bitcell of a similar size.


Rambus has developed single-ended signaling technologies to meet the memory system requirements of next-generation computing applications, while maintaining compatibility with current industry-standard DDR4 solutions. The next-generation R+ main memory architecture supports speeds up to 6.4Gb/s in a multi-rank, multi-DIMM system. Memory module upgrades are the most common way to increase capacity in a system, but the number of modules supported on a DDR4 memory channel drops at high data rates due to degraded signal integrity. This problem has led to a change in topology from multiple DIMMs per memory channel to a point-to-point topology that only supports a single DIMM per memory channel. This makes a DDR4 memory system difficult to scale and non-ideal for most server, workstation and high-end PCs. Memory access granularity also suffers as data rates increase due to the disparity between the interface and core access speeds. The result is an increase to the core prefetch and a sub-optimal transfer size for future multi-core and graphics computing applications. The R+ technologies address these issues by enabling single-ended signaling to go beyond DDR4 in a power-efficient and cost-effective manner.

- Nick Flaherty
  EE Times

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