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I/O sync techniques for complex embedded designs

Posted: 15 Apr 2014     Print Version  Bookmark and Share

Keywords:automation systems  VxWorks  FPGAs  ADC  ENOB 

This clock jitter will impact the measurement accuracy. As seen in figure 2, the error introduced by the clock jitter is related to the input signal's frequency. High frequency signals have a greater voltage difference (dv) for the same amount of clock jitter (dt).

The equivalent number of bits (ENOB) is a metric of how much resolution a measurement system can maintain. The more clock jitter the system has, the lower the ENOB will be. Figure 3 shows how ENOB is related to the input signal frequency and the amount of jitter in the sampling clock. Each line represents a different number of nanoseconds of jitter on the signal. As the signal frequency increases, the ENOB decreases for a given amount of jitter.

Figure 2: Voltage difference dependent on frequency.

Figure 3: Equivalent number of bits.

Heterogeneous I/O synchronisation
Embedded systems used in control and measurement applications typically have to measure a variety of signal types. Depending on the measurement range, bandwidth and signal conditioning requirements, different sensors may be measured by different types of hardware. The methods used to synchronise these different types of hardware vary by the type of ADC used – successive approximation register-based (SAR ADC),or sigma-delta based (Sigma-Delta ADC) – and the system architecture..

A successive-approximation ADC uses a comparator to successively narrow a range that contains the input voltage. At each successive step, the converter compares the input voltage to the output of an internal digital to analogue converter which might represent the midpoint of a selected voltage range. At each step in this process, the approximation is stored in a successive approximation register (SAR). This type of ADC has a CONVERT pin that is used to tell the ADC when to take a sample. Each pulse on the CONVERT pin causes the ADC to take one sample. Synchronising multiple SAR ADC's can be achieved by providing the same CONVERT signal to each ADC.

A sigma-delta ADC oversamples the desired signal by a large factor and filters the desired signal band. Generally, a smaller number of bits than required are converted using a Flash ADC after the filter. The resulting signal, along with the error generated by the discrete levels of the Flash, is fed back and subtracted from the input to the filter. This negative feedback has the effect of noise shaping the error due to the Flash so that it does not appear in the desired signal frequencies.

A digital filter (decimation filter) follows the ADC which reduces the sampling rate, filters off unwanted noise signal and increases the resolution of the output (sigma-delta modulation, also called delta-sigma modulation). This type of ADC uses a free-running oversample clock to acquire its data. The ADC returns data at a rate determined by the decimation filter that is synchronous to the oversample clock. Synchronising multiple sigma-delta ADC's can be achieved by providing the same oversample clock to each ADC.

Synchronising multiple SAR ADCs
How well you can synchronise different ADC's will depend greatly on the level of control you have over the conversion and data transfer (figure 4). Let's take a system that is attempting to synchronise two different pieces of hardware that both contain SAR ADC's. One piece of hardware has some setup that must be performed before the conversion.

This can be setting input multiplexers, changing gain settings, input settling time or some other operation that the hardware needs before it is ready for the conversion. The other piece of hardware is always ready for a conversion. For both of the ADC's, there is some time spent transferring the data back to the control unit after the conversion. The conversion process is started by a software command that triggers both pieces of hardware simultaneously.

Figure 4: Conversion timing delays.

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