Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Embedded
 
 
Embedded  

I/O sync techniques for complex embedded designs

Posted: 15 Apr 2014     Print Version  Bookmark and Share

Keywords:automation systems  VxWorks  FPGAs  ADC  ENOB 

When the action, such as data acquisition, is started on the master node, a trigger signal is shared with the other nodes to begin the action. Variables like trace length can affect how tightly synchronised the signals actually are. A tightly configured system will use timers and advanced FPGAs to slightly move the edge of each individual trigger line to help achieve synchronisation within a few hundred picoseconds. Figure 6 shows an example of a physically connected system, along with the clock and trigger lines.

Physically distributed system synchronisation
A physically distributed system has nodes that perform I/O in multiple physical locations. Examples of this include everything from temperature sensors spread across a factory to health monitoring sensors on turbines spread across a wind farm to voltage and current sensors on a power grid spread across a continent. These physically distributed cannot share a common clock to synchronise their I/O. Instead, they must use other methods of synchronisation.

Figure 6: Physically connected synchronisation system.

Time referenced systems. The blue portion of the precision versus distance graph shows the precision achievable by time-referenced synchronisation. In a time-referenced system, protocols such as GPS are used to convey time information across greater distances than are prqactical with cabling. This time information is used by each system node to determine the present time and create a clock based on that reference. You can use a future time event, which is when an action starts after a defined time is reached, to trigger an action across all nodes simultaneously. Figure 7 shows a time-referenced synchronisation system.

Figure 7: Time-referenced synchronisation system.

Another method of visualizing this transfer of time data via time protocols is the clock tower/wristwatch analogy (figure 8). Think of the master node as being the clock tower and the slave nodes as being the people in a small town. Everyone in the town must be at work at 8:00 a.m. and they all have their own wristwatches. But each person's wristwatch could be different, and there might be confusion over the correct current time. If each person looks at the clock tower and resets, or synchronises, his or her wristwatch to the clock tower time reference, then everyone has the right time and arrives at work on time. The same conveyance of time information takes place in time-referenced systems.

Figure 8: Time reference and time source.

Time protocols
Time protocols are the tools you use to transport time information across large distances.

Pulse per second (PPS) is a simple form of synchronisation that outputs a pulse once a second. The rising edges of two consecutive pulses should be exactly one second apart. The signal does not contain information about the specific time of day or year. The pulse width is generally 100 ms, but many receivers allow the user to specify the pulse width, as long as it is less than one second. Figure 9 shows a PPS signal.

Figure 9: Pulse per second.

IRIG-B – This older protocol was developed in the 1950s and is used to transmit time data. The signal is similar to PPS, but instead of a single pulse once a second, IRIG-B sends coded bits that make up a data frame that is one second long. This data frame presents time information in seconds, minutes, and days and provides a status byte. IRIG-B has a synchronisation precision of tens of nanoseconds.

Figure 10 shows how time is sent using IRIG-B. The entire frame is only one second long. It is based on pulse-width modulation (PWM), where a 25 per cent duty cycle represents a 0, a 50 per cent duty cycle is a 1, and a 75 per cent duty cycle is a Pause (P) to separate the pulses for seconds, minutes, days, and the status. Two pause cycles (R in this diagram) signify the end of a timestamp. Figure 6 shows an IRIG-B signal, which is read from right to left.

Figure 10: IRIG-B.

IEEE 1588 – IEEE 1588 is a packet-based protocol that you can use over Ethernet (figure 11). It defines a standard set of clock characteristics and value ranges for each characteristic. By running a distributed algorithm, called the best master clock (BMC) algorithm, each clock in the network identifies the highest-quality clock; that is the clock with the best set of characteristics.

 First Page Previous Page 1 • 2 • 3 • 4 • 5 Next Page Last Page



Comment on "I/O sync techniques for complex embe..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top