Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Processors/DSPs

How to achieve persistent DRAM on processors

Posted: 14 Apr 2014     Print Version  Bookmark and Share

Keywords:Freescale  PowerQUICC  QorIQ  processors  DRAM 

Freescale PowerQUICC III and QorIQ processors enable the user to force the DRAM into self-refresh mode, which allows the user to maintain data in DRAM while the processor is not available to refresh the DRAM array. This also eliminates the need for DRAM refreshes by the processor's memory controller. As a result, the memory controller can be put to sleep.

Practical applications range from enabling persistent storage of trace and crash records in DRAM through a processor reset to persistence of program and data in DRAM through processor sleep and low-power modes.

View the PDF document for more information.

Originally published by Freescale Semiconductor at as "Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors".

Comment on "How to achieve persistent DRAM on pr..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top