How to achieve persistent DRAM on processors

Freescale PowerQUICC III and QorIQ processors enable the user to force the DRAM into self-refresh mode, which allows the user to maintain data in DRAM while the processor is not available to refresh the DRAM array. This also eliminates the need for DRAM refreshes by the processor's memory controller. As a result, the memory controller can be put to sleep.

Practical applications range from enabling persistent storage of trace and crash records in DRAM through a processor reset to persistence of program and data in DRAM through processor sleep and low-power modes.

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Originally published by Freescale Semiconductor at www.freescale.com as "Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors".