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Grasping DC power integrity

Posted: 25 Mar 2014     Print Version  Bookmark and Share

Keywords:PCB  Power integrity  signal integrity  AC  DC 

When I first learned to design digital electronics and lay out a PCB, I was taught to put all the 74-series chips and the microprocessor in neat rows. The rule of thumb was to add a single 0.1µF ceramic capacitor for decoupling to each device, and sometimes to add an additional 1µF tantalum or electrolytic capacitor for the micros in parallel. I never worried too much about getting power to each device—using a 20 or 30 mil trace was enough for a chip that never drew more than 100 mA, along with the classic interdigitated +5V/GND grid.

Of course, power electronic designs are a different ballgame. I always took a lot more time, care, and planning with power supply and amplifier designs—making sure to use proper (star) grounding and keeping high-current loops as tight as possible.

Some of this was more than 20 years ago, and, of course, there has been a lot of development in the decoupling and power network topic since then. More elaborate and carefully placed decoupling setups have to be designed for each new silicon process node, each new chip package generation, and each new PCB design as they are packed more densely with parts. It's getting difficult to find room for all the rule-of-thumb decoupling caps. And with BGA packaged devices down to 0.4 mm pitch that can draw several amps of current during use, it's getting really difficult to plan and design a good power network on the PCB. Whether we like it or not, power integrity is a challenge that all PCB designers and engineers have to address.

Power integrity is discussed a lot these days. But a lot of the talk is really on the signal integrity side—I call it AC power integrity—which is really about the impedances of the power network at high frequencies. This deals with how the decoupling is designed, as well as return paths for high-speed signals. This is nontrivial, but I don't want to simply regurgitate this already very commonly discussed topic. I want to get down to DC. Why? Well, it just seems to me that learning to walk before trying to run is a good idea, so let's talk DC power integrity.

At face value, DC power integrity seems to be a simple enough topic—you just need to make sure there's enough copper to get the necessary current to each device on the board. But that's just at face value. When you start to work with fine-pitch device packages, the manufacturing constraints and power requirements of said devices are almost completely at odds with each other. Not only is it difficult to get the required current to all the power pins, but you are also working with multiple supply voltages. This means that, unless you want a high-layer-count PCB, you will have to get power to your devices through various split planes, and that's where the trouble begins.

Before I go too far down into the rabbit hole of designing power distribution networks, how can you tell if you have a power integrity problem? These issues are sneaky little blighters, like cockroaches that scamper into the crevices when you turn on the light. The moment you try looking for these issues is the moment they can't easily be reproduced. But you may have a power integrity issue if any of these symptoms occur in your assemblies.
 • The CPU is resetting unexpectedly or when a high-utilisation thread enters execution.
 • Memory devices keep failing their content retention/corruption tests.
 • Analogue front-end circuits are randomly inaccurate or out of design specs.
 • CPU or FPGA devices fail catastrophically.
 • FPGA configurations are corrupted during powerup.
 • PCB vias go open circuit after a number of use cycles, or maybe even at first power on.
 • Production PCBs suffer blistering in common locations.
 • PCBs suffer delamination in common locations.
 • Trace or polygon neckdowns are fusing.
 • Laminate or solder mask material is discoloured in some regions of the PCB.

These symptoms fall into two broad categories of DC power integrity problems. For example, items 1-5 are the more sinister misbehaviours caused by transient voltage drops across the board. Sometimes they can be fixed with better decoupling, but when you're talking DC, only adding more copper will really improve the design. Items 6-10 are more serious power integrity issues where current density regularly exceeds the safe limits for temperature rise. The board is suffering from localized heating, or copper is outright fusing.

There are some useful tools for avoiding these sorts of problems before prototype, such as the IPC-2152 conductor sizing charts. I would say every design must begin with these charts as the basis for power network design rules for the PCB layout. However, some designs now approach a part density that make it necessary to design on the edge and work with means and duty cycles to make sure the board doesn't fail.

The bottom line is that DC power integrity means making sure each device in the design gets the power it needs without suffering the problems mentioned above—all while ensuring a reliable power network on the PCB.

In my forthcoming blogs, I want to go into a bit more depth about these different DC power integrity problems and look at some specific ways to avoid them right from the start. In the meantime, I welcome your comments and questions.

About the author
Ben Jordan is senior manager of content marketing strategy at Altium.

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