Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Tips for accelerating SoC physical design at RTL

Posted: 26 Mar 2014     Print Version  Bookmark and Share

Keywords:System on Chip  physical implementation  SoC  DFT  SDC 

The increasing complexity of modern System on Chip (SoC), the design effort associated with the increasing pressure on silicon cost, and the pressure associated with shortened schedule requirements make it essential to use innovative implementation approaches to optimise silicon area and ensure a short and predictable timeline.

Silicon design usually suffers from the disconnection of needs between logical designers and physical architectures. This disconnect leads to costly iteration loops to reconcile incompatible options taken by design teams working in isolation. In this article, we will review the essential points to consider in order to ensure a smooth transition between the logical and physical worlds.

Logical and physical implementation context
Let's have a look at the situation. At the beginning of the design process, the SoC's initial representation is captured based on the functional description of the circuit and the logical architecture suitable to achieve the functionality and performance. This is usually expressed as shown in figure 1.

Figure 1: Typical SoC today.

When it comes to physical implementation – with the assumption that flattening the entire design is not an option due to the size of modern SoCs and the limited capacity of place and route tools at deep sub-micron nodes – we have to determine a suitable hierarchy for the backend implementation to result in an optimal design.

The traditional approach was to mimic, in the physical domain, the hierarchy inherited from the RTL coming from the logical assembly of the SoC (figure 2a). The main drawbacks with this approach are the huge complexity of the top-level floor plan, the overall synchronisation of the sub block's development and the final timing convergence.

Figure 2: Different physical implementation strategies of the SoC.

Recently, it became more common to harden some specific parts of the design, creating the adequate level of hierarchy in the RTL and flattening the remaining part of the SoC (figure 2b). The benefit of this methodology is that it limits the complexity of the top-level floor plan. However, since the bus fabric is implemented at the top level, timing convergence remains a challenge, and the wire dominant nature of the bus potentially makes the silicon utilisation less than optimal.

To further improve the previous approach, a designer can choose not to have any logic at the top level of the circuit by pushing all the circuit components, including bus fabric, within the physical partitions leaving only inter-partition connections at top level (figure 2c). The designer could alternately connect those physical partitions by abutment (inserting feedthroughs for the connections having to traverse a physical partition). This approach leads to an extremely optimised usage of the silicon (as the wire dominant nature of the bus is merged within blocks which are more gate intensive), along with a predictable timing closure, provided a number of good design practices have been followed.

Tips for optimised soc realisation
At the beginning of the implementation process, it is important to identify the degrees of freedom that exist: The IO ring (typically predefined) provides strong constraints to the placement of interface blocks, while the elements that primarily connect to the internal bus have more flexibility for their location within the die.

1 • 2 • 3 Next Page Last Page



Comment on "Tips for accelerating SoC physical d..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top