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Minimise metastability with User Grey Cell approach

Posted: 17 Mar 2014     Print Version  Bookmark and Share

Keywords:IPs  EDA  User Grey Cell  clock domain crossing  CDC 

User Grey Cells can be created by the FPGA vendor, by the IP provider, or by the user. When produced by the FPGA vendor or the IP provider, the User Grey Cell will be included in their IP distribution. In the case of the FPGA vendor, it can be included within Blue Pearl's software release. Meanwhile, at the usage point, the designer will specify where the models are installed.

Illustration of User Grey Cell using a simple design
Let's use a loop-back FIFO design to illustrate the usage of a User Grey Cell. The FIFO is generated from Xilinx CoreGen and the end user can choose, such as in Case 2 below, to use one of the Blue Pearl Software shipped User Grey Cell models for CDC analysis.

Since the FIFO is generated, there is no RTL description of its functionality. While parsing the design, the FIFO will be represented by a Black Box unless the user specifies the path to the User Grey Cell model, as shown in figure 4.

Figure 4: Specifying the path to the User Grey Cell model.

Case 1: CDC analysis using a Black Box methodology
In this case, the FIFO was treated as a Black Box during the CDC analysis. The results are displayed in the CDC viewer window (figure 5). It is empty since no CDC issues were found.

Figure 5: CDC results for Case 1.

Now, this can give a false sense of confidence, leading the designer to believe that the design is free from any CDC errors.

Case 2: CDC analysis using a User Grey Cell methodology
In this particular case, the end user created a User Grey Cell model for the FIFO as shown in figure 6.

Figure 6: User Grey Cell for the generated FIFO.

This time the user indicated that a User Grey Cell exist for the FIFO and then ran the CDC analysis. This time, the results in the CDC Viewer (figure 7) are quite different. Here we see six CDC violations.

Figure 7: CDC results for Case 2.

Moreover, we can check if the FIFO is connected properly in the design. One of the CDC violations in this example is due to the "full" signal not being synchronised with "rdclk" in the "read" domain.

What's the take-away?
Designers who are frustrated with—or who have been burned by—unexplained chip failures caused by metastability issues now have an alternative to the Black Box method of verification. Using Blue Pearl's relatively easy-to-use User Grey Cell methodology, the chances of missing the metastability-causing CDC problems can be significantly reduced.

Have you been burned by metastability issues in one of your FPGA or ASIC/SoC designs? If so, please share your experiences in the comments section, including the ways in which you tracked down and identified the problems.

About the author
Shakeel Jeeawoody is with Blue Pearl Software.

To download the PDF version of this article, click here.


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