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Standard logic process cuts SRAM power

Posted: 06 Mar 2014     Print Version  Bookmark and Share

Keywords:Silicon Basis  SRAM  standard logic process  28nm silicon 

Silicon Basis, has developed a novel way of building static memory on a standard logic process that slashes the power by 50 percent without sacrificing any aspect in area or speed. The company sees two key advantages for its technology it can save half the power consumption and it can go below the bit cell voltage of the foundry memories.

This allows the memories to be powered by the same voltage source as the logic and so eliminates the need for a second DC-DC converter. It also makes the technology foundry independent and scalable to new technologies such as FinFet, added de Souza. The company has produced all the models needed and is now working on 28nm silicon to prove the implementation.

"Fundamentally memory has some real problems everyone does it the same way," stated de Souza. "They all take the TSMC arrays and put them together. We use our own bit cell so we are not restricted to the foundry's Vmin which is a huge advantage. Dropping the voltage makes a huge difference."

All of this comes from a new way of looking at the design of the cell that is currently being patented.

"No one has seen this way of designing SRAM before," he said. "We are talking to the experts in memory design and no one has seen this way of putting memory together. It's all using standard rules and standard CMOS. It's an architectural difference that means we don't need to use sense amps and because we are using logic rules we can go down to the logic voltage floor and possibly below that."

"Our cell size is about the same as the high speed cell from the foundry," said Rob Beat, founder and CTO of Silicon Basis and designer of the new cell. "There's a compromise on area in the array but because the periphery is more efficient we are competitive in area especially on the smaller RAMs."

The architecture brings advantages with the compiler that are not to be underestimated, he noted.

"Our single port compiler also outputs a one port register file," he said. "Because of the way the bit cell is designed we can use the same bit cell for dual port so the dual port compiler will do the dual port register file and asynchronous dual port memory." This avoids the problems of having up to five different compilers for each process technology with a significant support burden, he continued.

The technology has been characterized on the TSMC 40nm node and outperforms the high speed bit cell, said de Souza. "This took us a little bit by surprise as we didn't design for speed," he said. "We did a lot of work at 40nm but what we are seeing from customers is that 28nm HPM is going to be a major node and we think there will be more new designs starting on 28nm than on 40nm."

The technology is also fully compatible with FinFet vertical structures being used in TSMCs 16nm process node. "Our technology will work very nicely with FinFet right out of the box," he said.

The technology has previously been used by Beat to develop low power FPGA fabric but has attracted more interest for the SRAM compiler. "For me, Silicon Basis starts here," said de Souza.

- Nick Flaherty
  EE Times Europe

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