Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Embedded

PLLs in IC-based clock distribution system (Part 3)

Posted: 27 Feb 2014     Print Version  Bookmark and Share

Keywords:phase-locked loop  PLL  clock distribution  jitter  noise 

In Part 1 and Part 2 we dealt with the role of phase-locked loops in IC-based clock distribution systems and how phase noise and jitter affect their performance. In this article we will look at the many other noise sources due to thermal, shot, flicker, white, reference, voltage controlled oscillator, phase detector, frequency divider, and charge pump effects and how to deal with them.

The many sources of phase noise
Generally oscillators are characterized in terms of their single-sideband phase noise (figure 1). Phase noise (dBc/Hz) is plotted as a function of offset frequency f0 on a logarithmic scale.

Figure 1: Oscillator phase noise in dBc/Hz vs. frequency offset.

The actual curve is approximated by a number of regions, each having a slope of 1/fx, where x = 0 corresponds to the "white" phase noise region i.e. slope of the curve is 0 dB/decade. For x = 1, phase noise region is called "flicker" and its slope is –20 dB/decade. Similarly, other regions correspond to higher values of x. A region with a higher value of x is closer to the carrier frequency.

Figure 2 shows a plot of phase noise for a PLL-based clock generator. It should be noted here that this plot can be approximated to different noise regions as shown in figure 1.

Figure 2: Phase noise in dBc/Hz vs. frequency offset.

The output signal of an oscillator, no matter how good it is, will contain all kinds of unwanted noise signals. Some of these unwanted signals are spurious output frequencies and harmonics. The noise can be random or deterministic in both the amplitude and phase of the signal. Here we will look into the major sources of some of these unwanted noise signals.

Oscillator noise performance is characterized as jitter in the time domain and as phase noise in the frequency domain. Which one is preferred, time or frequency domain, may depend on the application. In radio frequency (RF) communications, phase noise is preferred while in digital systems, jitter is favoured. Hence, an RF engineer would prefer to address phase noise while a digital engineer wants jitter specified.

1 • 2 • 3 Next Page Last Page

Comment on "PLLs in IC-based clock distribution ..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top