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Intel Labs all set to tie loose ends

Posted: 12 Feb 2014     Print Version  Bookmark and Share

Keywords:Intel Labs  interconnect  Brian Krzanich  network 

Intel Labs' new director, has announced that he will run a tight ship in his first public outing, a press conference describing papers on low-power interconnects and security techniques it will present at this week's International Solid-State Circuits Conference. According to Wen-Hann Wang, who took on the job last year, the 1,000-person group aims to "be very disciplined, take risks, fail fast, improve innovation yield, encourage new ideas... and be tightly aligned with Intel's business units."

Wang took over the labs from Justin Rattner last year about the same time Brian Krzanich took over as chief executive of Intel. Wang joined Intel in 1991 as a Pentium Pro platform architect, but spent most of his time as a research manager in Intel's microprocessor research lab in 1995 and later as a director of its emerging platforms lab and then its circuits and system research group.

Wen-Hann Wang

Wang referred to the "new Intel Labs" under Krzanich as a focused group working on "high risk, high reward projects relevant to the company's business groups." We are not an ivory tower or country club, but a 21st century industrial research lab... able to touch people's lives though our products," he said.

"It sounds more like advanced development than some of the research we seen in the past," said Nathan Brookwood, principal of market watcher Insight64 in Saratoga, Calif., who sat in on the call.

Vivek De, director of the circuit research group in Intel Labs, described a handful of research papers Intel will present at ISSCC this week. Several showed progress designing transistors operating at near-threshold voltage to reduce power consumption, a hot topic at ISSCC in recent years.

In one paper, Intel will describe a technique for generating and storing a unique random key on a chip that cannot be discovered by physically probing it. The key can be used for a variety of security functions including authentication. The approach leverages process variations that create unique delays when passing through a circuit array.

Another paper describes a 256 node on-chip network offering 20.2Tb/s of aggregate bandwidth. It uses packet-switching techniques to set up a link and circuit switching to stream data between nodes.

A third paper describes a serial interconnect over shielded copper pair wires that delivers 32Gbs/s over a 1.5m distance including cables, board traces and connectors. The link is suitable for use in consumer systems, the researcher added.

- Rick Merritt
  EE Times

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