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FPGAs/PLDs

Quick start guide for Sonoma ZedBoard

Posted: 19 Feb 2014

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Keywords:Sonoma Xilinx ISE ZedBoard Zynq

Here is a high-level overview of the steps required to quickly get the Sonoma design running by downloading and running the FPGA project.

The top level of the hardware design is a Xilinx PlanAhead Project (.prr) for Xilinx PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides FPGA/board net connectivity, and instantiates the wrapper that carries the Zynq Processing System. This is supplied as a Xilinx software development kit (SDK) project that includes a demonstration software application to evaluate the Sonoma subsystem reference design. The lower level c-code driver routines are portable to the user's own software project.

View the PDF document for more information.

Originally published by Maxim Integrated at www.maxim-ic.com as "Sonoma (MAXREFDES14#) ZedBoard Quick Start Guide".