Quick start guide for Fremont ZedBoard

The top level of the hardware design is a Xilinx PlanAhead Project (.PRR) for Xilinx PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides FPGA/board net connectivity, and instantiates the wrapper that carries both the Zynq Processing System and AXI_MAX11100 custom IP core that interface to the Pmod port. This is supplied as a Xilinx software development kit (SDK) project that includes a demonstration software application to evaluate the Fremont sub-system reference design. The lower level c-code driver routines are portable to the user's own software project.

In this application note, a high-level overview of the steps required to quickly get the Fremont design running by downloading and running the FPGA project. Detailed instructions for each step are provided in the following pages.

View the PDF document for more information.

Originally published by Maxim Integrated at www.maxim-ic.com as "Fremont (MAXREFDES6#) ZedBoard Quick Start Guide".