Quick start guide for Fremont Nexys 3

The top level of the hardware design is a Xilinx ISE Project Navigator Project (.XISE) for Xilinx ISE version 13.4. The Verilog-based HDL design instantiates the MicroBlaze core, the support hardware required to run the MicroBlaze and the peripherals that interface to the Pmod ports. This is supplied as a Xilinx software development kit (SDK) project that includes a demonstration software application to evaluate the Fremont sub-system reference design. The lower level c-code driver routines are portable to the user's own software project.

Here's a high-level overview of the steps required to quickly get the Fremont design running by downloading and running the FPGA project. Detailed instructions for each step are provided in the following pages.

View the PDF document for more information.

Originally published by Maxim Integrated at www.maxim-ic.com as "Fremont (MAXREFDES6#) Nexys 3 Quick Start Guide".