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DCD unveils IP Core featuring configurable SPI parameters

Posted: 06 Feb 2014     Print Version  Bookmark and Share

Keywords:Digital Core Design  SPI parameter  IP Core  EEPROM  DRAM 

Digital Core Design has announced an IP Core that the company said performs communication and exchanges data between external serial EEPROM and CPU's RAM interface. According to the firm, the DEEPROM implements configurable SPI parameters such as serial clock prescaler, SPI mode and CS hold/setup.

Aimed at DRAM designs, the DEEPROM's contents are accessible to the CPU in the same manner as a common SRAM memory, but require READY input to expand the time access. "Our proprietary core allows to map serial EEPROM in processor memory space and control it as the parallel memory," said Jacek Hanke, DCD's CEO. The controller automatically sends all control instructions and read/write memory locations. As for the CPU, the EEPROM is being connected to it through the DEEPROM. Moreover, it's visible and controlled as parallel SRAM with long access time. DEEPROM's big advantage is that the core has been designed to operate with popular 25XXX SPI Serial EEPROMs from Atmel, Microchip," added Hanke.


When all other factors are sustained, memory controller is becoming crucial. That's why DCD's IP Core has been developed to ensure the most accurate data flow. It was designed in accordance with JEDEC specification and all the other industry standards, which summarized together make the DEEPROM very small, efficient, with no internal tri-state buffers and signals IP Core.

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