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JTAG/boundary scan for electronic assembly devt

Posted: 30 Jan 2014     Print Version  Bookmark and Share

Keywords:JTAG  boundary scan  BGA packaging  transmission lines  EMS 

JTAG/boundary scan has become an increasingly important application, in particular in the development departments of small and large companies. On one hand this is due to the enormous potential the technology provides and, on the other hand to the problems increasingly compact assemblies and components place on test technologies with respect to mechanical access. Modern BGA packaging and high-speed transmission lines call for new approaches.

JTAG/boundary scan provides excellent and efficient utilisation opportunities. But what are the extraordinary benefits for designers? What must be considered in assembly design to apply Boundary Scan? These topics are dealt with in the following article.

JTAG/boundary scan in development?
Is this really necessary? Isn't it enough that designers – under consideration of some restrictions − must plaster their boards with test points? Must designers now write tests themselves? What is the return on this effort? To fully understand, a few things must be made clear.

What is required for test generation? It is essential to know what component types are used, and how the component pins are interconnected. Each component type must be assigned to a related model. For example, there is a model for each Boundary Scan component describing the IC's Boundary Scan structure, a so called BSDL (Boundary Scan Description Language) model. Depending on the vendor, there are additional models describing non-Boundary Scan components such as RAM or driver ICs. But that's the only precondition to generate board tests.

The test system provides the models, and the required CAD data are limited to a net list and a component list. These can be found in the schematic that is usually available at an early board development stage. The advantage: problems that may occur in test generation can be solved easier, and test-depth-inconvenient designs can be changed extremely fast and simple. However, this is not all.

Generated tests are available already for the first prototypes. They can be tested with the same quality as the 0-series and finally the serial product – the same test depth, the same pin-level fault information. Now that the test bus necessary for Boundary Scan is available on the UUT (unit under test), e.g. via a connector, this interface can be used to load FPGA or CPLD components or to put the boot loader into the program flash. The resulting savings are apparent.

That doesn't sound that bad, does it? But why are the designers to generate tests? These are test engineering tasks, incl. all associated problems!

However, consider the following points.

1. The designer knows the board best!
 • Starting with the component designations ...
 • Where are the focal points?
 • Is high test effort justified

Design changes for test depth increase are quickly implemented – resulting in an assembly ideally designed for test

This is all leading to efficient test generation and finally efficient testing.

2. The first prototype can already be tested by the same methods as the serial product. Therefore, the test depth is the same. Additionally, the same pin-level fault information is provided

This leads to an efficient initiation of prototypes and 0-series under serial conditions.

3. Ideal interface for EMS
 • The test archive is simply passed to the EMS. The contract manufacturer doesn't have to coordinate or balance test generation and test scope.
 • Test changes are implemented very fast.

For contract manufacturers, there is an extremely small amount of test effort (only the test equipment must be provided) leading to minimal costs.

All in all, there are a significant number of advantages a designer benefits from to a large extent. That obviously compensates the manageable effort in test generation.

What is JTAG/boundary scan?
JTAG/boundary scan is a standardised electric test method (IEEE Std. 1149.x). Stimulating and measuring the single circuitries on assemblies is no longer executed via predetermined test points and its connected metrology, but rather Boundary Scan cells integrated into a component. The IC architecture is shown in figure 1.

Figure 1: Boundary scan component.

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