Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Networks
 
 
Networks  

Be a decoupling capacitor network expert (Part 2)

Posted: 30 Dec 2013     Print Version  Bookmark and Share

Keywords:decoupling  capacitor  placement  layout  PCB 

When we left my previous article on the topic of decoupling, we were well on the way to understanding the behaviour of a real capacitor, the temperature at which I like my beer, and how to go about designing a decoupling capacitor network. What we had not addressed was the somewhat tricky aspect of where our decoupling capacitors should be located.

Whenever I talk to people about decoupling, they all say that the capacitor should be placed as close to the device as possible. However, very few people can actually tell me why this is or at what point close enough becomes too far away. As engineers, we need to understand what drives the placement of these components. Using this knowledge, we can define a series of rules regarding placement and layout such that the layout engineer is not told simply to put them as close as possible. The lack of clear guidance can hurt the complexity of the design, the complexity of the manufacturing, and the cost of the circuit board.

A key aspect of decoupling is controlling the inductance associated with both the tracking and the mounting of the capacitor. Though the capacitor stores the charge, the inductance determines the speed at which this charge can be delivered from the capacitor. Therefore, reducing the inductance loop is the most important aspect to consider when placing a capacitor.

This starts with the very design of the surface mount technology capacitor mounting pads within your PCB library. Ideally, the mounting via should be located as close as possible to the pad (though not within the pad, unless you are using micro-via technology). If space permits, it is better to use multiple vias per pad to reduce overall inductance. You definitely do not want long, thin tracks from the solder land to the via. Also, do not be tempted to share vias between capacitors.

The inductance loop is defined as the loop created between the mounting via and the connections to the voltage planes. For this reason, when you define the stack of your board and assign layers to power and ground, you need to assign higher-priority power planes (those with higher current demands from the device being decoupled) to be higher in the stack. This reduces the vertical distance the current needs to travel before reaching the plane.

When implemented correctly, the mounting inductance will be similar in value to the equivalent series inductance. This will have an impact on the resonant frequency (RF) of the capacitor, so it should be included in the RF calculation. As the inductance increases, the RF—not the self-resonant frequency, because the mounting inductance is included—will be reduced.


1 • 2 Next Page Last Page



Comment on "Be a decoupling capacitor network ex..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top