Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Memory/Storage

How to configure CoreNet Platform Cache as SRAM

Posted: 26 Dec 2013     Print Version  Bookmark and Share

Keywords:CoreNet Platform Cache  CPC  SRAM  Linux  DRAM 

This document discusses the software methods to configure the CoreNet Platform Cache (CPC) as high performance SRAM for use by Linux applications.

The CPC is a CoreNet-compliant target device that can serve as a general purpose write-back, an I/O stash, a memorymapped SRAM device, or any combination of these functions. As a general purpose cache, the CPC manages allocations and victimisations to reduce read latency and increase bandwidth for accesses to backing store (DRAM). As an I/O stash, the CPC can accept and allocate writes from an I/O device in order to reduce latency and improve bandwidth for multiple read operations to the same address. As an SRAM device, the CPC acts as a low-latency, high-bandwidth memory that occupies a programmable address range.

View the PDF document for more information.

Originally published by Freescale Semiconductor at as "Configuring CoreNet Platform Cache (CPC) as SRAM".

Comment on "How to configure CoreNet Platform Ca..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top