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IC design in FinFET tech: Evolution or revolution?

Posted: 10 Dec 2013     Print Version  Bookmark and Share

Keywords:FinFET  22 nm  EDA tools  MOSFETs  interconnect modelling 

All major foundries have announced FinFET technologies for their most advanced processes. Intel introduced this transistor at the 22 nm node, TSMC for their 16 nm process, and Samsung and Globalfoundries are introducing it for their 14 nm processes. As with any new process technology, the most important question to an IC designer is "What does this mean to me?"

New, smaller process technologies means the designer will benefit from reduced power consumption, better area utilisation, and other traditional improvements that come from semiconductor scaling. Along with those advantages, there is the learning cost to understand the new design rules, parametric differences, and new or enhanced methodologies that must be implemented to design at the new node. The benefits have always justified the costs until now. Will that still be true with FinFETs?

Like any other new technology, FinFET processes have a cost associated with learning how to design with them. Because FinFETS are a completely different transistor, the question is—will this change be evolutionary (typical learning cost) or revolutionary (significant learning cost). The answer depends on your perspective.

Evolutionary
The first thing to keep in mind is that, for most foundries, the back end of line (BEOL) configuration at 16 and 14 nm is the same as the 20 nm node. 20 nm saw the introduction of double patterning (DP), which had a significant impact on the design and manufacturing community. DP drove changes to design flows and was the catalyst for changes to EDA tools ranging across design implementation, verification, parasitic extraction, and analysis.

Fortunately, the challenges of DP are in the recent past. Triple or multi-patterning is coming, but not for the current FinFET processes. Since BEOL is the same as 20 nm, designers need to learn and understand the changes for the front end of line (FEOL) geometries. Figure 1 shows a representation of a FinFET device with a single "fin," although most FinFET devices will have multiple fins.

Figure 1: FinFET with single "fin." (Source: Globalfoundries)

Upon seeing these devices for the first time, most designers ask the following questions:

 • How do I design this?
 • How many fins should a device have?
 • What should the size/spacing of the fins be?
 • Where can I get the information I need to understand the geometry vs. electrical performance trade-offs?
These are tough questions! In general, designers—especially digital designers—consider width, length, and area as parameters in evaluating the trade-off between transistor configuration and electrical performance. The nature of FinFET design could dramatically change all that. Fortunately, most foundries have taken this into consideration, and they have developed a design methodology for FinFET process that is the same as 20 nm and above.

That's right—for this first generation of FinFETs, designers do not design/develop the fins (unless you are an SRAM designer). As with previous nodes, IC designers will develop transistors by defining the width, length, and area of the device. Design implementation, verification, extraction, and analysis tools will decompose the layout into the fins per the specification of the foundry, and then perform the necessary analysis to do physical verification, parametric and parasitic calculations, and even perform geometric fill and circuit simulation.

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