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EE Times-India > EDA/IP

Synopsys, CEVA teamed up to improve base station apps

Posted: 14 Nov 2013     Print Version  Bookmark and Share

Keywords:Synopsys  CEVA  base station  handset  DSP 

Synopsys Inc. and CEVA Inc. have collaborated to deliver highly optimised implementations of the CEVA-XC DSP cores aimed at the high-performance needs of base station applications and the low-power requirements of handset applications. CEVA used Synopsys' DesignWare High Performance Core (HPC) Design Kit to optimise its DSP for performance, power and area, achieving an eight per cent improvement in performance at 1.3GHz maximum operating frequency for its base station application and reducing leakage power by up to 13 per cent for its handset application, compared to previous implementations in the same technology, indicated the companies.

The DesignWare HPC Design Kit is a suite of optimised high-speed and high-density memories and logic libraries that allow SoC designers to optimise their processor cores for maximum speed, smallest area, lowest power, or for an optimum balance of the three for their specific application.

The CEVA-XC DSP architecture features a combination of Very Long Instruction Word (VLIW) and Vector engines that enhances typical DSP capabilities with advanced vector processing. The scalable CEVA-XC architecture offers a selection of highly powerful communication processors, with four generations to date (CEVA-XC321, CEVA-XC323, CEVA-XC4210 and CEVA-XC4500) widely licensed by leading vendors with over 20 design wins to date. The CEVA-XC architecture targets a range of communication applications and use cases including LTE-Advanced handsets, wireless infrastructure, WiFi stations and access points, cable modem, satellite modem and more.

Synopsys' DesignWare HPC Design Kit is an add-on to the DesignWare Duet package of embedded memories and logic libraries. The Duet package contains all the physical IP elements needed to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimisation Kits (POKs), as well as options for overdrive/low voltage process, voltage and temperature corners (PVTs), multi-channel cells and memory built-in self-test (BIST) and repair. The HPC Design Kit adds fast cache memory instances and performance-tuned flip-flops that enable speed improvement for processor cores of up to 10 per cent over the standard Duet package. To minimise dynamic and leakage power as well as die area, the HPC design kit provides area-optimised and multi-bit flip-flops as well as an ultra-high density two-port register file, which reduces area and power by up to 25 per cent while maintaining processor performance. Optimised design flow scripts and expert core implementation consulting services are also available to help design teams achieve their processor and SoC design goals in the shortest possible time.

The Synopsys DesignWare HPC Design Kit is available from Synopsys. The CEVA-XC Family of DSPs are available from CEVA.

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