Global Sources
EE Times-India
EE Times-India > EDA/IP

Mitigating antenna effect in IC design

Posted: 15 Nov 2013     Print Version  Bookmark and Share

Keywords:VLSI  Antenna Effect  power dissipation  Plasma Induced Gate Oxide Damage  PID 

Over several decades, the density and speed of ICs have risen exponentially, following a trend described by Moore's Law. While it is accepted that this exponential improvement trend will end, it is still not clear that exactly how dense and fast integrated circuits will get by the time this point is reached. With the increasing density and Gate oxide width reducing with each technology node, many effects which were common in VLSI are becoming important and difficult to manage. One of those effects is Antenna Effect. The semiconductor technology has been continuously improved over the past two decades and has led to ever smaller dimensions, higher packaging density, faster circuits, and lower power dissipation.

Figure 1: The collected net charges are channeled to the gate.

Antenna effect
The Antenna Effect or Plasma Induced Gate Oxide Damage is an effect that can potentially cause yield and reliability problems during the manufacturing of MOS integrated circuits. Presently Lithographic processes for IC fabrication use 'Plasma etching' (or 'dry etching'). Plasma is an ionized/reactive gas used to etch. It allows super control of pattern (shaper edges / less undercut) and also allows several chemical reactions that are not possible in traditional (wet) etch. But life is not always so good. Several unwanted effects also accumulate. One of them is the charging damage.

Plasma charging damage refers to the unintended high-field stressing of the gate-oxide in MOSFET during plasma processing. During Plasma Etching high amount of charge can collect on poly and metal surfaces. Through capacitive coupling, large electric fields may develop over gate oxides, resulting in stresses that cause oxide breakdown and shifts in threshold voltage Vt of the device. The collected net charges are channeled to the gate as shown in figure 1 where it is neutralized by the current tunnelling across the gate-oxide.

Clearly, the size of the conductor exposed to the plasma plays a role in determining the magnitude of the net charge collection rate and therefore the tunnelling current. This is the so called "antenna effect". The area ratio of the conductor to the oxide under the gate is the antenna ratio. The antenna ratio, in a rough sense, is a current multiplier that amplifies the tunnelling current density across the gate-oxide.

For a given antenna ratio, a larger tunnelling current is supported when the plasma density is higher. Higher tunnelling current means higher damage. For the conductor layer pattern etching processes, the amount of accumulated charge is proportional to perimeter length. For ashing processes, the amount of accumulated charge is proportional to area. For contact etching processes, the amount of accumulated charge is proportional to area of via.

Classically, the antenna ratio (AR) is defined as the ratio of total area and/or perimeter of conducting layer attached to gate, to the total gate area.

1 • 2 • 3 Next Page Last Page

Comment on "Mitigating antenna effect in IC desi..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top