Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Power/Alternative Energy
 
 
Power/Alternative Energy  

Techniques for power-efficient rendering

Posted: 04 Nov 2013     Print Version  Bookmark and Share

Keywords:Mobile processors  game console  SoC  application processor  Computer graphics 

Mobile processors nowadays are improving at an astonishing rate, and consequently delivering visually stunning user experiences at less than 3 watts of power consumption.

Just how is it that mobile processors running at 5 per cent of the power of a game console, can produce the kind of graphics realism we had previously come to expect only from game consoles?

It's all about the pixel and making it shine, without drinking a lot of power. Let's look at a few of techniques being used in modern SoC application processors to achieve these fantastic results.

Figure 1: There are techniques being used in modern SoC application processors to achieve these fantastic results.

Creating realism within the constraints of mobile devices
Computer graphics (CG) features like hardware tessellation, geometry shading, and high dynamic range (HDR) are developed on big PCs and workstations and then migrated to the mobile platforms. The mobile platforms are getting larger screens and more powerful processors, the elements needed for advanced CG. The challenge is how to get stunning, real-time, workstation-class graphics in a battery-powered device that can run for eight or more hours and not become too hot to hold.

The first step in any power management system, whether it's a phone, your home, or a PC, is to turn things off that aren't being used.

With rudimentary power management under control, developers of the SoCs looked into algorithmic opportunities to deliver realistic images. With the semiconductor suppliers working in their research labs, and with game developers, movie studios, and university computer scientists, clever techniques have emerged over the past two to three years.

Tiling, chunking, and tile-based deferred rendering
In 1991, computer scientists at Microsoft Research launched the Talisman project to investigate new techniques to improve rendering time while scaling screen resolution and colour depth. The results were promising, but the hardware design proved to be too challenging for the semiconductor process technology available. However, several ideas from the project were successfully developed, including tiling and deferred rendering (originally developed by Pixel Planes at the University of North Carolina). Microsoft used that knowledge to develop it for Talisman. Software renderers, like Reyes developed at Pixar, also employed tiled methods, prior to Microsoft.

In tiling, the image is broken up into small sections and updated only when the image within them changes. In addition, tiling uses a tiled Z (depth) buffer to determine if a portion of a polygon is visible, and if not, it's not rendered. The process is similar to a traditional 3D graphics pipeline, but reduced to the size of a small tile. Tiling can also take advantage of early Z buffering (buffering early in the pipeline, after scan conversion, but before shading), to further reduce work.

Figure 2: Z-depth rejection rending example. (Source: Qualcomm)


1 • 2 Next Page Last Page



Comment on "Techniques for power-efficient rende..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top