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Arasan rolls eMMC v5.0 Total IP Solution

Posted: 30 Oct 2013     Print Version  Bookmark and Share

Keywords:Arasan Chip Systems  eMMC v5.0 I/O PADs & PHY IP  embedded mobile storage  smartphone  tablet 

Arasan Chip Systems Inc. has introduced what it boasts as the most complete solution for the latest eMMC standard: Embedded MultiMediaCard (eMMC), Electrical Standard (5.0). The eMMC v5.0 Total IP Solution includes eMMC 5.0 host and device IP, software stack and driver, verification IP and the analogue PHY and PAD set required for embedded mobile storage for smart phones and tablets.

The Arasan PAD set fully supports the eMMC 5.0 HS400 specification at 3.3V output. At 200MHz, the required clock speed of HS400, a DLL is required to ensure accurate data transfer. The HS400 mode uses a 200MHz clock and DDR signalling to achieve a maximum bandwidth of 400MB/s. The Arasan eMMC PHY IP includes an analogue PHY comprising three DLLs needed for tuning, strobe and hold time management, described the firm.

JEDEC published the latest version of the eMMC v5.0 standard that defines new functionalities and enhancements for embedded mass-storage flash memory widely used in consumer electronics including tablets, smartphones, GPS systems, e-readers and other mobile computing devices. The previous version of the standard that supported speeds up to 200 Mega Transfers per Second permitted a digital implementation. eMMC v5.0 doubles the bandwidth to 400MB/s, but requires analogue components (I/O PADs and PHY). At this performance level, interface timing tuning, which has been a feature of eMMC, must be done in an analogue PHY instead of using a simple tapped delay line.

First, Arasan's 28nm general purpose I/O PADs are multipurpose PADs that can be programmed to operate in different modes: 1) Output with predetermined source/sink impedance, 2) Open drain, 3) Input, 4) Tristate and 5) Weak pull up or pull down. The I/O PADs are specially designed to seamlessly integrate with Arasan's eMMC 5.0 host controller IP.

The PAD is designed using TSMC's 28HPM process technology. With wide performance/leakage coverage, the 28HPM process is geared for many applications from networking, tablets, to mobile consumer products, added the company.

DLL works in conjunction with a 32 tap delay line and multiplexing logic to align the placement of clock edges. It uses the 28nmHPM process and is intended for core voltage of 0.9V and I/O voltage of 3.3V. Also, the Arasan solution provides a calibration I/O PAD that automatically goes to a low power state after resistor value selection. This architecture minimises power and area in a design.

Arasan's 28nm eMMC v5.0 PAD and PHY offering is available now.





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