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Get rid of risks in real-time software tasks

Posted: 31 Oct 2013     Print Version  Bookmark and Share

Keywords:simulation  software  validation  simulators  VisualSim 

Simulating the data and control flow software tasks and threads can boost response time and improve reliability of real-time applications. To gain maximum advantage, the software simulation must be performed during the specification phase and needs to include power and performance attributes.

The simulation of the software process will deliver a quality product specification that meets the timing requirements and will be within the resource budgets. To achieve this potential and deliver quality software systems, the effort must be effectively tied with good quality timing and the hardware architecture specification.

The impact of missing timing deadlines or incorrect response to failure can be catastrophic to the embedded and real-time system. In this article, we simulate two highly distributed applications on a multi-core architecture and optimise the performance, reliability and power consumption.

The growing concern for safety and security requires the software tasks to be tested for many forms of data, network, and functional errors. Testing with implemented software is extremely complex because of the huge prototype cost and the inability to replicate the errors. Moreover, changes identified after implementation will delay the delivery cycle, create potential malfunctions, and affect product quality. Early simulation can identify a number of implementation errors while identifying issues that would need to be tested.

Industry challenges addressed
Application of hardware-enabled software process is a major consideration in the aerospace, defence, and automotive industries because of the need for safety, reliability and adequate protection against failures. A hardware-enabled software task is the ability to visualise the operation of the software tasks on a target hardware platform prior to development of the software code. Current approaches are limited to analytical techniques. These provide either a rough estimate or a worst case/best case timing, neither of which take into consideration realistic system operation.

An alternate approach to this evaluation of software processes is the use of digital simulation to model the software processes as a series of control and data-flow that are mapped on hardware topologies. Good representative patterns of the traffic stimuli are applied to this model and the corresponding response times, power consumed, and correctness of the expected output is measured. These reports are used as constraints for downstream implementation. As this analysis is performed prior to the development of any implementation flow definition, the constraints become the validation metrics for software testing.

This important software thread design will meet the performance (latency and throughout) and power deadlines. In this effort, the hardware platform is represented as a combination of the communication topology, computation technologies, and the scheduling algorithm. The faults introduced for testing include late arrival of sensor data at the interface, modified data at the memory location, overwritten schedule table, and wrong sequence of task sequence.

Simulation technology
In our analysis of real-time software at CMR Design Automation, we've used the commercial system-level design software VisualSim Architect, which is a modelling and simulation environment with a graphical block diagram editor, simulators, and model construction libraries, including those for representing the hardware, schedulers, and software processes.

When a simulation has completed, our designers receive a series of graphical and textual reports that trace the software tasks, the application response times, hardware utilisation, power consumption, and cumulative activity. This has been used at various companies to architect the hardware based on the activity of software processes, threads, memory assignment, and IO activity.

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