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CEVA, ARM unveil vector floating-point DSP

Posted: 21 Oct 2013     Print Version  Bookmark and Share

Keywords:CEVA  vector floating-point DSP  CEVA-XC4500  AMBA 4 ACE  WiFi offloading 

CEVA has collaborated with ARM to create a vector floating-point DSP specifically intended for advanced wireless infrastructure solutions. The CEVA-XC4500 includes a baseband-dedicated instruction set architecture (ISA), IEEE-compliant floating point support on full vector elements delivering up to 40GFLOPs performance, comprehensive multi-core support, a fully cached architecture and hardware managed coherency, detailed the firm.

The core, which uses as little as 100mW for LTE 2x2 Pico-Cell baseband processing, is fully cacheable with an advanced data cache that includes hardware cache coherency via ARM's AMBA 4 ACE, and includes an advanced system interconnect using a mix of ARM AMBA 4 compliant buses and fast interconnect (FIC) buses to other system blocks. It also comes with a set of LTE eNodeB libraries.

Several important emerging technologies such as heterogeneous cellular networks (HetNet) and cloud RAN (C-RAN) require more powerful, higher performance processing solutions to deliver on their promise. The CEVA-XC4500 DSP runs at up to 1.3GHz on a 28nm process and the vector DSP engine supports Fixed Point and Floating Point (IEEE compliant) ISA on full vectors. This enables software-defined architecture with a mix of optimised hardware engines for DSP offloading and a range of tightly coupled acceleration blocks (TCE—Tightly Coupled Extensions) are available. Automated data traffic management offers fully parallel hardware acceleration management with no DSP intervention while dynamic scheduling enables symmetric system design with runtime task allocation based on system load

The core is able to address any wireless infrastructure use case, including baseband: from small cells (Pico, Metro) to macro base stations and cloud RAN (C-RAN); WiFi offloading; wireless backhaul; and remote radio heads.

The CEVA-XC4500 DSP architecture is supported by the CEVA-Tool-box software development environment, incorporating Vec-C compiler technology for advanced vector processors and enabling the entire architecture to be programmed in C. The Integrated simulator and profiler provide accurate modelling of the entire system including: caches, DMA controllers, interfaces, tightly coupled extensions and more, stated the company. In addition, CEVA-Tool-box includes a set of LTE/LTE-Advanced eNodeB libraries introduced for the CEVA-XC4500 for the first time, which complements the existing comprehensive library suite for WiFi, TD-SCDMA, WCDMA and HSPA+.

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