Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > RF/Microwave
 
 
RF/Microwave  

Data converter IP targets advanced 28nm node

Posted: 14 Oct 2013     Print Version  Bookmark and Share

Keywords:data converter  wireless communication  ADC  DAC  CMOS 

Cadence Design Systems Inc. has unleashed a portfolio of ultra-fast, low-power analogue intellectual property (IP) products geared to enable the next generation of high-speed wired and wireless communications applications. According to the company, the products meet the needs of designers working with emerging high-speed protocols such as WiGig (802.11ad), which runs on a 60GHz spectrum with potential data throughput up to 7Gb/s, as well as LTE and LTE Advanced.

The Cadence data converter family includes the 7bit 3GSPS dual ADC and DAC, 11bit 1.5GSPS dual ADC and 12bit 2GSPS dual DAC. The data converter IP cores can be easily combined to form a complete analogue front end (AFE) IP solution. The Cadence family of IP addresses key applications in wired/wireless communications, infrastructure, imaging and software-defined radios, the firm noted.

The ADC IP cores are developed with a parallel successive approximation array (SAR) architecture, producing extremely fast and scalable sample rates. High effective-number-of-bits (ENOB) values are achieved with a unique implementation and built-in background auto calibration, producing more accurate conversion and consistent performance. The Cadence IP includes features such as differential data inputs, reference and timing generator, internal offset correction, and voltage regulators for improved supply noise immunity, detailed the company.

The DAC IP cores use a current switching architecture and include a digital multiplexer and FIFO for easy integration into an SoC. The DACs include digital gain control and all required reference circuitry.

All the IP includes multi-level power-down modes for additional power savings, a built-in analogue test bus for design testability, and single-ended CMOS or differential current-mode logic (CML) clock inputs for a flexible clock interface.

The Cadence IP provides matching dual channels for communication systems where these are desired, simplifying implementation and reducing risk, and a standard CMOS process target for easy manufacturing.





Comment on "Data converter IP targets advanced 2..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top