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Arasan rolls out MIPI M-PHY 3.0-compliant IP

Posted: 10 Oct 2013     Print Version  Bookmark and Share

Keywords:MIPI M-PHY 3.0  Camera Serial Interface 3  M-PCIe 

Arasan Chip Systems Inc. has released what it touts as the industry's first MIPI M-PHY 3.0-compliant IP supporting multiple speed gears and a range of high-speed interfaces for mobile applications. The MIPI M-PHY version 3.0 multi-gear analogue IP PHY supports a range of protocols including Universal Flash Storage (UFS), Camera Serial Interface 3 (CSI-3), USB Super-speed Inter-chip (SSIC) and M-PCIe interfaces, detailed the company.

The Arasan M-PHY IP offers support for high-speed GEAR1, GEAR2 and GEAR3 supporting a variety of different protocol and performance requirements up to 5.8Gb/s per lane. In addition, the MIPI M-PHY IP is complaint to MIPI Alliance Standard for M-PHY specification version 3.0, supports M-PHY Type I systems, high-speed differential and low-speed PWM modes, configurable termination, error detection and on-chip clock generation.

The highly configurable M-PHY analogue IP core enables designers with a scalable solution to easily meet increasing high performance data rates, modular architectures for IP re-use and customer proven silicon IP. Arasan's MIPI M-PHY analogue IP implementation is optimised to support high-performance while meeting the low power, small area and optimised electromagnetic interference (EMI) performance requirements of mobile applications.

In addition, Arasan ships a UFS Hardware Validation Platform (HVP) enabling early validation by emulating a Host or Device system at the interface protocol level.

The M-PHY analogue Total IP solution is available, including host and device digital controllers (UFS 2.0, CSI-3), Verification IP, Linux OS-based hardware platforms and all of the customer-required support files and documentation.





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