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Adjust regulator to optimise DSP power budget

Posted: 08 Oct 2013     Print Version  Bookmark and Share

Keywords:power budget optimisation  energy consumption  DC/DC  VID programmer  DSP 

Power saving and power budget optimisation at the system level are crucial in many applications. For example, data centre operators struggle to cap energy consumption, portable equipment designers seek reduced current draw for longer battery life, and communication systems require lower operating temperature for increased reliability.

Key specifications in power supply design are now viewed through the prism of:
1) Maximising efficiency over the entire load current range; and
2) Adaptively scaling the output voltage according to the needs of the load.

Output voltage adjustment using voltage identification (VID) is one technique to cater to these objectives. Of course, VID programmability is already widely adopted in DC/DC core-voltage regulators for microprocessor applications, based on the well-known adaptive voltage scaling (AVS) specifications from Intel or AMD. However, these VID controllers are characteristically exclusive to and tailored around ultra-high current requirements based on the multi-phase buck topology.

Digital signal processors (DSPs), FPGAs, and ASICs now have similar capability to attain maximum power reduction based on such devices' activity, power and clock domain configurations, modes of operation, and operating temperature. While digital-based pulse-width modulator (PWM) controller solutions with VIDare available to meet this demand, a need clearly exists to digitally adjust the output voltage of the ubiquitous, analogue-controlled, point-of-load (POL) regulators. In doing so, an analogue power implementation, perhaps already designed-in and bench tested, is easily repurposed to meet system-level power budget and cost targets that might otherwise be unattainable.

Digital output voltage adjustment
Reflecting the ascendant interest in the foregoing design goals, a VID programmer is now available as an application-targeted standard product (ATSP) from TI. Designed to complement an analogue-oriented POL DC/DC solution, the LM10011, shown in figure 1, includes a precision, digitally programmable current D/A converter (IDAC) with mode selectable 4- and 6bit VID interfaces. An accurate DC current from the IDAC_OUT pin, proportional to a 4bit or 6bit digital input word, is sourced into the feedback (FB) node of the output voltage regulation loop. As the input word counts up, the IDAC_OUT current is reduced, adjusting the output voltage setpoint higher based on the regulator's feedback resistors. The FB node typically is held at a constant voltage by the analogue control loop's error amplifier.

Figure 1: Conventional POL regulator paired with a current DAC to a 6bit digital VID interface.

Paramount in this implementation is compatibility of the VID solution with the analogue POL regulator design. The POL is effectively deployed as a slave for the DSP. As it works out, the IDAC solution enables DSPs and other digital loads to realise their full power savings capability to reduce power consumption, for example in communications infrastructure applications. In fact, this VID solution is primarily intended to operate alongside any POL regulator to adjust the core voltage (VCORE) of a VID-enabled processor, such as the KeyStone-based multi-core DSP.

Figure 2: Multicore DSP/SoC platform with core rail powered by 500kHz synchronous buck regulator inclusive of VID-controlled adjustability.

DSP core power
Illustrated in figure 2 is a schematic of a multi-core DSP with core voltage, CVDD, derived from a synchronous buck POL regulator. The power stage comprises a 15-A voltage-mode regulator, 560-nH inductor, and ceramic input and output filter capacitors [2]. The 6bit VID command from the DSP facilitates adjustment of the output voltage, VOUT, based on a concomitant change in DSP performance requirement.

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