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FPGAs/PLDs  

Altera upgrades IP line targeting 28nm devices

Posted: 03 Oct 2013     Print Version  Bookmark and Share

Keywords:Altera  IP core  FPGA  Serial RapidIO  Interlaken 

Altera Corp. has completed the latest upgrade to its portfolio of IP cores geared for 28nm FPGAs and SoCs. According to the firm, the IP cores have been enhanced to deliver 15 per cent timing margin for faster timing closure, which allow customers to quickly integrate multiple IP cores into their designs and get to market faster.

Altera offers a comprehensive portfolio of internally developed IP cores and strategic partner IP cores that support the company's FPGA and SoC product lines. The portfolio of IP cores contains popular external memory protocols, protocol interface IP, and video and image processing IP, stated the company.

Some of the most recent protocol interface cores released include 50G/100G/150G/200G Interlaken, targeting wireline applications; Serial RapidIO Gen 2 up to 6.25Gb/s per lane, targeting wireless applications; 10/100/1000Mb/s 1588 Ethernet MAC cores, enabling precise time synchronisation on Ethernet networks; and SerialLite III Streaming, enabling high bandwidth, low latency point-to-point serial data transfers across various transmission media.





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