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Step up to C to boost embedded R&D

Posted: 07 Oct 2013     Print Version  Bookmark and Share

Keywords:embedded systems  hardware/software co-design  ESL  SystemC  TLM-2.0 

We are all eager to cut down the cost of embedded system design, while increasing quality and decreasing time-to-market. However, as embedded systems become more complex and sophisticated, the traditional design process is taking up too much time. It is simply not agile enough to achieve the results as rapidly as we need.

Since the 1990s, efforts to improve the R&D of embedded systems using hardware/software co-design have yielded limited co-development processes. The R&D has tended to centre on specific types of hardware design, and still with separate departmental teams involved; hardware and software. As a result, prototypes still require an integration phase, along with the risks that this process incurs, and multiple coding languages are used, resulting in a constant need for recoding.

The starting point for a more agile approach to development is to work at a higher level of abstraction, in this case, ESL, or electronic system level.

By taking advantage of the SystemC library definitions and TLM-2.0 interface standards—both part of standard IEEE 1666—we can use a single language, C/C++. This allows us to create a fully-modelled functional software representation of a hardware/software SoC design based on a mix of processors, software, communication links (AXI interconnects), memories, and other IP cores. Thus, the various tasks of the requested embedded application can be implemented in the SoC as either hardware or software, according to quality-of-results (QoR) requirements based on performance, power consumption, and hardware resource utilisation, following a true hardware/software co-design approach.

Under this approach, the hardware/software co-design process is conducted from the very start of a SoC embedded system project. The application is first broken down into multiple tasks; otherwise, a single large task will end up as a single software or hardware implementation without the benefit of optimisation. Before introducing details of any target architecture platform, the tasks need to comprise an algorithm that is a functional specification of the application, which must be validated through behavioural simulation.

Once the algorithm is deemed sound, the functional specification is then mapped to an initial design configuration, for a chosen architecture platform of processors (including RTOS) and interconnects. Some tasks will be targeted for software implementation while others will be targeted for hardware. A design exploration process ensues, where successive design configurations are analysed based on QoR constraints. Real co-design takes place while exploring different design configurations and adjusting the hardware/software partitioning.

This process can be facilitated by an automation technology which retargets the same C/C++ models from hardware to software, or vice-versa, without recoding for the other medium, resulting in a rapid and agile process.

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