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Effective hardware/firmware co-design (Part 2)

Posted: 19 Sep 2013     Print Version  Bookmark and Share

Keywords:Buffer  embedded systems  interrupt  hardware  firmware 

One of the factors contributing to the success of embedded systems products is performance. Is it fast enough to meet the customer's requirements and expectations? But is it cheap enough that the customer will buy it?

Putting a V-8 engine on a lawn mower will definitely provide sufficient performance; however, it will be too expensive for the consumer. Performance must be weighed against cost.

Previously discussed in Part 1 were trade-offs between polling a status bit and waiting for an interrupt. Interrupts allow firmware to work on something else until the event occurs, and then be notified immediately when it does occur.

But judicious use of interrupts is required to avoid bogging down the system with interrupts occurring too frequently. Likewise, other aspects of the hardware/firmware interaction require judicious designs to ensure optimal performance.

This section discusses a few techniques to maximise the performance at the hardware/firmware interface without incurring too much cost in the platform.

Increasing the Buffer. Increasing the buffer size for I/O data allows more data to be transferred with fewer interrupts. But the question is: how big should the buffers be? It depends on the application. Table 1 contains some guidelines.

Table 1: Guidelines on buffer sizes.

These and other system requirements may compete against each other in driving the buffer sizes and will require striking a proper balance. Increasing the buffer size does require more space on the chip, which must be taken into consideration. The overall silicon space of the buffer as a percentage of the whole chip is a factor. Doubling the size of the buffer from 8B to 16B has a small impact on the chip. But doubling the size of the buffer from 8 KB to 16 KB will impact the space requirements on the chip.

Best Practice Tip: Size receive and transmit buffers appropriately for efficient communication between hardware and firmware.

Working Ahead. It may not be just a matter of making the buffer size bigger. Once the buffer fills up, firmware has to deal with it.

But firmware will do so whenever it is allowed, given its priority compared to other tasks that need to run. After the block fills up one buffer, must the block wait around until firmware empties that buffer? Or is there another buffer that the block can start filling up?

If the block can work ahead, it can keep busy. The size and number of buffers dictate how far ahead the block can work. The same applies in the other direction. If firmware can queue up a bunch of work for the block, firmware can forget about it for a little while.

DMA controllers can help by providing chaining capabilities, allowing immediate continuation from one chunk of memory to the next. Buffers and chaining allow for continuous processing of data from one chunk to the next assuming that associated settings in configuration registers stay the same.

However, if configuration settings need to change between chunks, the block needs to finish with one chunk and stop, and then allow firmware to change the settings and start the next chunk. Stopping between chunks and requiring firmware interaction will not work if the system requires moving from one chunk to the next in a timely fashion.

An example of this type of system is a LaserJet printer where the raster image for one page is maintained in several chunks. Once the mechanical gear train starts moving paper and scanning the laser, it cannot stop. So the block has to move from one chunk to the next within 50 ns. Firmware cannot step in, set up, and start up the next chunk during that time. The solution to this is to double-buffer the necessary configuration registers, or basically have two sets of registers, the working set, and the hold set.

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