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Issues in power mgmt with internal regulation

Posted: 09 Sep 2013     Print Version  Bookmark and Share

Keywords:SoCs  regulator  Bandgap References  Process-Voltage-Temperature  power-up 

Issue seen with the improper enable logic of the regulators and the suggested solution: One classic issue which is observed and is sometimes left unattended is, when exactly the SUPPORTING regulator is switched ON. Let us consider one such problematic case and how exactly this can be rectified.

The main regulator is switched ON as soon as the external voltage supply (which is the supply required by the regulator to function) crosses its POR (Power On Reset) level POR_EXTERNAL_SUPPLY. The main regulator then begins to build the voltage supply, slowly ramping it up.

The logic of the pd (power down) of the SUPPORTING regulator may be such that the SUPPORTING regulator is turned ON when this regulated voltage supply reaches its POR level, POR_REGULATED_SUPPLY (the MAIN regulator still ramping it up). This minimum voltage level at which the SUPPORTING regulator comes out of its power down state is what is problematic. This is because as soon as the SUPPORTING regulator comes out of its power down state it follows the constant regulated voltage supply value and takes its own output to that level.

Since the output of the two regulators are shorted (as shown in figure 2) so the SUPPORTING regulator ends up pulling the regulated voltage value to the final static value from its POR value in a few nanoseconds time interval which poses serious ESD threats to the system (Refer figure 3a).

The solution suggested to this problem here is simple and easy to implement.

 • The power down of the SUPPORTING regulator should be gated with the reset state signal of the SoC.
 • By doing this the Supporting regulator is not able to come alive until the System is out of the Reset state (Refer to figure 3b) and the main regulator is up and stable.
 • This ensures that, when the System encounters any current surges due to the digital IPs (which are in power down condition when the system is in Reset) the Supporting regulator is alive and ready to support the MAIN regulator as desired.

Figure 3a: Issue in vdd_lv ramp when the PD of Supporting Regulator is gated with POR of vdd_lv.

Figure 3b: Solution to the issue in figure 3a by gating the pd of Supporting Regulator with Reset_b.

Figure 4a: Main Regulator alone unable to handle the instability due to increase in frequency causing LVD conditions.

Figure 4b: Auxiliary Regulator supporting Main Regulator to avoid LVD conditions during increase in system frequency.

Regulation level of the individual regulators
Regulation level of the MAIN and AUXILIARY regulator with respect to each other: The next issue with multi-regulated systems is the regulation level of the individual regulators and how the overall system is one that gives maximum stability in voltage level and is seasoned to any dynamic current changes in the system.

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