Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Samsung uses Synopsys RTL Synthesis sol'n

Posted: 06 Sep 2013     Print Version  Bookmark and Share

Keywords:Synopsys  Samsung  Design Compiler Graphical  RTL Synthesis  mobile device 

Samsung Electronics has deployed SynopsysDesign Compiler Graphical product with an aim to reduce power and area to deliver more competitive SoCs for the mobile market.

Advanced technologies in Design Compiler Graphical, a key component of Synopsys’ Galaxy Implementation Platform, including congestion optimization, advanced placement-based timing optimization and physical guidance to Synopsys’ IC Compiler place and route solution, enable Samsung to achieve their challenging design goals and meet their schedule.

Design Compiler Graphical addresses the needs of challenging designs at both advanced and established nodes. It includes technology shared with IC Compiler to consider physical effects such as routing congestion and RC variation with metal layers during synthesis, to drive superior timing, area and power results. The advanced placement-based optimization of Design Compiler Graphical delivers 10 percent faster timing, minimizing the need for Low-Vt cells that have better timing but higher leakage power consumption. It passes physical guidance to IC Compiler, bringing synthesis timing and area results to within five percent of layout for a faster design closure. Design teams across all market segments are deploying Design Compiler Graphical and realizing its significant frequency, area, power and productivity benefits.





Comment on "Samsung uses Synopsys RTL Synthesis ..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top