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Understanding configurable IP and VHDL NULL range

Posted: 29 Aug 2013     Print Version  Bookmark and Share

Keywords:SoC designs  IP cores  configurability  VHDL  NULL range 

Over the past 15 years, IC designs have become increasingly complex. Users these days have growing demands for features and functions from various forms of electronics, such as consumer, automotive and medical. Designing everything from scratch will require more manpower as well as more time for delivering the product. In order to meet the required time-to-market in the current competitive scenarios, all real world SoC designs use IP cores.

This has resulted in a business model where some companies specialised only in selling IP cores. It does not only help in designing the system, but it also reduces verification efforts. Since individual IP cores would have been verified by the provider, the SoC designer can concentrate mostly on the system.

IP configurability
IP core providers would want to provide their cores in a way that a particular core can be used in multiple applications, thereby requiring a high degree of configurability. The configurability could be reflected as follows:
 • The functionality could be modified, e.g. whether the core is triggered on positive edge of clock or negative edge of clock. The SoC designer might be allowed to make a choice, either through some register setting or through value on some specific input pins.
 • Some additional output pins being available. The SoC designer would be allowed to make a choice, by not using some of these output pins.
 • The port/pin size could be customised to the specific design. This is usually done through generics (for VHDL) and parameters (for Verilog).

Consider the following VHDL code excerpt as an example. Here, the size of data port can be customised in each design application.

The following code segment shows how an application can change the port size for data.

VHDL allows two types of range specifications:
 • L to R: Ascending range. If L > R, then, this is called a NULL Range.
 • L downto R: Descending range. If L < R, then, this is called a NULL Range.

The L and R values themselves should usually be sufficient to denote the bus specification, as in Verilog. However, the need for to and downto to agree with the L and R values may create situations of NULL ranges.

As shown above in example code excerpt, VHDL generics are used to configure the bus widths which are passed from higher level of design hierarchy. In the given example code:

If NUM_BYTES=1, then the data width becomes 8bit ((1*8-1) downto 0).
If NUM_BYTES=0, then the data width becomes null range ie., ((0*8-1 downto 0) becomes (-1 downto 0).

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