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Designing LVDS interface between ADC and FPGA

Posted: 10 Jul 2013     Print Version  Bookmark and Share

Keywords:LVDS interface  ADC  FPGA  digital data 

In this application note, we describe the design considerations for designing the LVDS interface between the ADC and FPGA. It also provides details on LVDS Data Standards. LVDS (Low Voltage Differential Signaling) is a more widely accepted standard for ADCs digital data output along with LVCMOS. Timing analysis of LVDS data capturing into FPGA is beneficial to engineers who design with the ADC and FPGA interface. Even though this application note analyses the LVDS interface, with few modifications, this timing analysis can be applied to other differential standards.

View the PDF document for more information.

Originally published by Texas Instruments at as "Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Data Interface with FPGA".

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