Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Processors/DSPs

Cavium uses MIPSr5 architecture

Posted: 19 Jun 2013     Print Version  Bookmark and Share

Keywords:MIPSr5  Octeon III  multi-core processors 

Cavium Inc. is leveraging Imagination Technologies' Release 5 MIPS architecture (MIPSr5) features in its ultra-high performance 1-48 core Octeon III family of devices.

The MIPS64 architecture is already at the heart of a wide range of Cavium's Octeon processors, and now will also power Cavium's Octeon III family of 1-48 core processors that deliver over 100Gb/s of application performance per chip, and provide among the highest compute power of any standards-based communications processor chip with 120GHz of 64-bit compute processing per chip, Cavium said.

Jim Whittaker, EVP, processor group at Imagination commented: "With MIPS, Cavium has created some of the industry's highest performance and most advanced 64-bit multi-core processors for networking, wireless and storage. We're now working even more closely with Cavium to take MIPS, the industry's most successful and widely deployed 64-bit architecture, to even higher levels of performance and innovation. Imagination's ownership of MIPS has significantly increased the level of investment in, and support for, MIPS CPU IP core development across the entire range of 32-bit and 64-bit solutions, with a focus on hardware, software, tools and ecosystem. We are delighted that Cavium has reaffirmed its commitment to MIPS as a result."

"The MIPSr5 architecture enhancements from Imagination combined with Cavium's in-house design expertise will help create the most advanced MIPS 64-bit processor in the industry and will serve to further extend our leadership in the network infrastructure market," M. Raghib Hussain, corporate VP/GM and CTO, Cavium said.

Imagination noted that its family of MIPS processors are ideal for products where ultra low-power, compact silicon area and a high level of integration are required. MIPS processor IP cores and architectures range from ultra-low power 32-bit microcontrollers to scalable 32-bit and 64-bit multi-core solutions for advanced application and network processing platforms.

The seamlessly compatible MIPS32 and MIPS64 instruction-set architectures (ISAs) allow customers to port from one generation to the next while fully preserving their investment in existing software. MIPSr5 architecture incorporates important functionality including hardware virtualization and SIMD (Single Instruction Multiple Data) modules.

Comment on "Cavium uses MIPSr5 architecture"
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top