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Design solution aimed for Samsung's 14nm FinFET process

Posted: 05 Jun 2013     Print Version  Bookmark and Share

Keywords:FinFET  14LPE  physical design implementation  parasitic extraction 

Synopsys has showcased a new comprehensive design implementation solution that incorporates fast-field-solver technologies to model the effect of 3D structures for parasitic extraction, accurate high-performance models for device simulation, and comprehensive support for new rules for physical design implementation. The technology is specifically targeted for Samsung's 14LPE FinFET process.

Synopsys closely worked with Samsung to accelerate the adoption of new 3D FinFET devices for Samsung's 14nm process geometry.

"Our close collaboration with Synopsys is driven by a firm commitment to enable successful deployment of 14nm FinFET technology," said Kyu-Myung Choi, senior vice president, System LSI infrastructure design centre, Samsung Electronics. "With the complete, silicon-validated solution developed with Synopsys, we enable our customers to create new, innovative products by taking advantage of the power and performance benefits offered by this cutting-edge 14LPE process."

"Our delivery of a comprehensive design implementation solution for Samsung's FinFET process underscores our commitment to advance the state-of-the-art in semiconductor design," said Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys. "Deep collaboration is essential for us to address our mutual customers' FinFET needs. We have focused on foundational technologies, including 3-D parasitic extraction and device simulations, as well as delivery of FinFET-ready design implementation and in-design verification tools."

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