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DRC debugging issues in AMS/custom designs at 20nm

Posted: 03 Jun 2013     Print Version  Bookmark and Share

Keywords:design rule checks  DRC  double patterning  verification  Calibre RealTime 

To fix this particular odd-cycle violation, we need to break the interaction between the odd cycle of polygons. If we move the top edge of the bottom polygon down, Calibre RealTime provides immediate feedback showing that the error ring has grown to encompass the previous warning ring (figure 9). This error expansion occurs because the two polygons interacting at the location where we made the edit also interact in a second location, and breaking that first interaction did not completely fix the interactions of these three polygons.

To completely fix this odd-cycle violation, we need to break the separation between the three polygons by moving the edge of the rightside polygon, as shown in figure 10. As soon as that change is made, Calibre RealTime verifies that the odd-cycle violation is fixed by removing all error and warning rings.

Figure 9: Immediate feedback after attempted fix shows the error ring growing to encompass one of the previous warning rings.

Figure 10: Immediate feedback showing that odd-cycle violation has been accurately corrected.

Conclusion
The increase in number and complexity of design rule checks, as well as the addition of new interactive checks such as VD-DRC and DP checks, brings new challenges to DRC debug for custom designers. EDA vendors are providing innovative solutions that help custom designers improve not only their productivity, but also their design quality, by providing them with signoff-quality verification and debugging assistance within their design environment. With the ability to correct DRC errors in the design environment, and with the assistance of debugging "hints" for complex errors, custom designers now have more time to focus on improving their layouts, while still meeting their design delivery schedules.

About the author
Srinivas Velivala is a Technical Marketing Engineer with the Design to Silicon Division of Mentor Graphics, focusing on developing Calibre integration and interface technologies. Before joining Mentor, he was an IC designer, designing high-density SRAM compilers. Srinivas received a B.tech. in Electronics from Jawaharlal Nehru Technological University in Hyderabad, India, and pursued additional studies at Southern Illinois University in Carbondale, Illinois.

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