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Design, verify digital hardware with SystemC TLM

Posted: 20 May 2013     Print Version  Bookmark and Share

Keywords:SystemC  transaction-level models  high-level synthesis 

In summary, Fujitsu Semiconductor achieved 35% less area, 51% less power, and 35% better performance with 3x fewer lines of code than the hand-written RTL design, following the same design specification. This convinced them that HLS technology is ready not only for data-path designs but also for control-centric designs, which can include complicated bus interfaces like this data access controller. Raising the abstraction level allows designers to focus more on design exploration than RTL implementation, which can significantly improve both design productivity as well as QoR.

Verification methodology
To verify the design and analyse its data throughput and dynamic power consumption, Fujitsu Semiconductor created a comprehensive verification environment using Cadence Verification IP (VIP) for AMBA Protocols, including AXI3. They used this environment to debug and analyse both the SystemC TLM model and the HLS-generated Verilog RTL as shown in figures 3 and 4.

Figure 3: SystemC verification environment.

Figure 4: HLS-generated RTL verification environment.

For the verification effort, Fujitsu Semiconductor did not have to write any code at the signal level. All new code was written at the transaction level because the AXI3 VIP provides an abstract API for creating test scenarios, and provides checkers and coverage collectors for all AXI3 signal-level bus traffic.

The SystemC TLM was created without timing details for any AXI3 bus signals. They also created various test scenarios using the AXI3 VIP with some specific constraints and randomized constraints without any AXI3 bus signal timing details. The AXI3 TLM IP and AXI3 VIP helped them focus on functional design, verification, and debug, greatly simplifying the design and verification effort.

After C-to-Silicon Compiler generated the Verilog RTL, the team used the same verification environment to re-run the tests on the RTL and to analyse dynamic power. The verification environment with AXI3 VIP mimics an interconnect, helping to realistically analyse the data throughput and dynamic power consumption of the design.

Using the same test scenarios within the verification environment, the team considered different coverage items for the respective models. For the SystemC model, the team considered functional coverage (design features) and code coverage (line coverage). For the HLS-generated RTL, they considered functional (AXI3 protocols and design features), code (line and expression), and FSM coverage (state and arc).

For future design projects, Fujitsu Semiconductor expects to see benefits in shifting more verification effort to higher levels of abstraction. In particular, they believe that much of the verification can be completed at the SystemC TLM level without including the signal-level transactors, and that additional coverage metrics can be used at the SystemC TLM level.

Next steps for TLM and HLS at Fujitsu Semiconductor
In the near-term, Fujitsu Semiconductor is proceeding with final verification of the new SystemC data access controller design so they can replace the hand-written design in their systems, to take advantage of its significantly improved area, power, and performance. They also expect to apply SystemC TLM and C-to-Silicon Compiler HLS for additional design IP projects in their company because they believe this will help them become more productive and achieve better QoR.

In the medium-term, they are interested in exploring how to use the SystemC TLM model to unify the design and verification flow between hardware and embedded software. The AXI3 TLM IP from Cadence can be configured to automatically provide a SystemC TLM2 interface to external components. Using this feature, they expect to be able to use the synthesisable SystemC TLM models that they develop directly in SystemC TLM2 virtual platforms.

In conclusion, Fujitsu Semiconductor's experience showed that a design team can successfully use SystemC TLM in combination with C-to-Silicon Compiler HLS to significantly improve design and verification productivity, and to exceed the QoR that are achievable using traditional RTL entry.

About the authors
Stuart Swan, Qiang Zhu and Xingri Li are from Cadence Design Systems Inc.

To download the PDF version of this article, click here.


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