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Design, verify digital hardware with SystemC TLM

Posted: 20 May 2013     Print Version  Bookmark and Share

Keywords:SystemC  transaction-level models  high-level synthesis 

Line Count: The line count of the SystemC model is almost 1/3 the size of the hand-written RTL code for this design, which is significant because there were over 10,000 lines of RTL. Note that the line count for the SystemC model only represents customer-written code, since the AXI3 TLM model was provided within a SystemC library and is design-independent. For the hand-written RTL code, there was no reusable AXI3 code available. The large line count reduction with the TLM-based approach significantly reduced the coding effort and enabled designers to concentrate on exploring and optimising core functionality.

Performance: To compare performance between the models, Fujitsu Semiconductor measured average throughput using six different types of data transfers that cover the various types of burst transfers the design needs to perform. In all cases, the performance of the HLS-generated RTL was better than that of the hand-written RTL and, on average, the HLS-generated model had 35% better performance than the hand-written RTL.

The reason for this was that Fujitsu Semiconductor was able to take advantage of the higher abstraction level of the SystemC model and explore a range of micro-architecture implementations in C-to-Silicon Compiler, ultimately finding a more efficient micro-architecture than what had been implemented in RTL. With traditional RTL-based design entry, this type of exploration is almost impossible.

Area: Fujitsu Semiconductor used Cadence C-to-Silicon Compiler to generate RTL from the SystemC model and Cadence RTL Compiler to generate the gate-level netlist using their own production technology library. Table 2 shows the area comparison between the HLS-generated RTL and the hand-written RTL using the implementation with eight logical channels, across different clock frequencies.

Table 2: Design parameters.

Power Consumption: Fujitsu Semiconductor utilised clock gating optimisation in both C-to-Silicon Compiler and RTL Compiler to reduce dynamic power, then compared the dynamic power consumption results of each flow by simulating at the gate level. Table 3 shows the dynamic power reduction from the SystemC flow versus the hand-written RTL flow.

Table 3: Power comparison at 400MHz.

Design summaryFujitsu Semiconductor was able to realise the following benefits in using SystemC TLM and C-to-Silicon Compiler HLS for this design:
 • Designers did not need to explicitly describe the state machine as they did when hand-writing RTL, enabling a much more efficient description of the design.
 • Using the AXI3 TLM IP library enabled a huge time savings in implementing the complicated AXI3 protocol, so designers could concentrate on realising better algorithms and micro-architectures.
 • C-to-Silicon Compiler automatically generated RTL based on different technology libraries. Designers did not need to fine-tune the timing for the chosen target technology library.
 • Using SystemC TLM and C-to-Silicon Compiler HLS made it much easier to explore a couple of different design micro-architectures and measure the resulting QoR. This actually was the key factor in reaching a better implementation than hand-written RTL design.

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