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Design, verify digital hardware with SystemC TLM

Posted: 20 May 2013     Print Version  Bookmark and Share

Keywords:SystemC  transaction-level models  high-level synthesis 

Cadence has developed a library of synthesisable IP for use with C-to-Silicon Compiler, spanning common building blocks such as FIFOs, register files, bus interfaces such as AHB and AXI, and floating- and fixed-point math operations. These models are designed to be highly configurable, and provide good QoR when synthesised to gates.

The data access controller design described in this paper used the AXI3 TLM IP and FIFO models provided by Cadence, greatly accelerating the design process and delivering good QoR. By starting with the examples and design IP, a designer can quickly get a basic design working, and then incrementally modify it to meet all design requirements.

The AXI3 TLM IP provided by Cadence enabled Fujitsu Semiconductor's models to use a high-level API to access the AXI3 bus, while still providing access to all protocol features of AXI3. In addition, the AXI3 TLM IP can be configured to automatically provide a SystemC TLM2 interface to external models. This makes it possible to use a single model to drive the HLS flow, as well as for high-speed simulation in TLM2 virtual platforms, which is something Fujitsu Semiconductor will explore in the future.

Case Study: A data access controller design
While earlier HLS tools focused on datapath-oriented designs, Fujitsu Semiconductor applied C-to-Silicon Compiler and the AXI3 TLM models to a control-centric data access controller design. The design is described in simplified form here, since some aspects are proprietary. It contains 64bit AXI3 target and initiator interfaces and one to eight logical channels for data transfer. Figure 1 shows the block diagram of the design. It uses an AXI3 target interface to configure the registers for all logical channels for data transfer and an internal FIFO to store the data from the source address to destination address via the AXI3 initiator interface. The "ChReg" is a set of registers to store the configuration parameters for each logical channel, and the "CommonRegs" is a set of registers to store the configuration parameters for all logical channels.

Figure 1: Data access controller block diagram.

Table 1 shows the design parameters.

Fujitsu Semiconductor implemented the design in SystemC using the Cadence AXI3 TLM IP. To accurately compare with their existing hand-written RTL design, they implemented the SystemC model as follows:
 • Use the standard AXI3 protocols with the same parameters as the existing hand-written RTL design.
 • Implement the same behaviour between SystemC and hand-written RTL.
 • Generate different micro-architectures by the SystemC flow from the hand-written RTL to improve QoR and performance.
 • Write the SystemC model so that its micro-architecture could be easily reconfigured using C++ parameters.

Figure 2 shows part of the SystemC source code for the design that configures the AXI3 TLM write address channel of the initiator socket. Line 1 declares the payload of the write address. Lines 2 to 5 set the attributes of the write address payload with address, transfer length, burst types, and data size for the AXI3 TLM initiator. Line 6 uses a while loop to put the write address payload on the write address channel of the initiator socket "initiator_if.waddr" using a non-blocking function "nb_put(waddr)". Note that all of the details of the AXI3 signal-level protocol are hidden in the nb_put() function in the AXI3 TLM library, so that designers can simply use a put/get function call without having to worry about these details. This significantly improves the readability of the code and completely separates the behaviour from the interface protocols.

Table 1: Design parameters.

Figure 2: SystemC code to access AXI3 TLM initiator.

Design results
Fujitsu Semiconductor successfully implemented the design using SystemC and the AXI3 TLM IP models, and used Cadence C-to-Silicon Compiler HLS to generate RTL. The design passed simulation and functional verification, described in more detail below. They compared the implementation, QoR, and performance with the hand-written RTL design.

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