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Post-CTS clock path timing analysis, automation

Posted: 14 May 2013     Print Version  Bookmark and Share

Keywords:RTL  verification  clock tree synthesis 

Given below is the output of the procedure we developed to analyse the margin for pushing/pulling a clock branch. The procedure was told to analyse the clock for pushing by 0.2 time units. Given first is the deterioration in setup for each of the end-points. For each end-point, the setup slack before annotation and after annotation is given. As we can see, only one end-point goes negative and that too by very less amount. Similarly, there is no problem with respect to hold perspective. Hence, we may freely choose to push the clock branch by 200 ps.

 

Figure 3 shows the procedure to calculate the push/pull margin.

Figure 3: Flowchart to generate report for analysis of push/pull margin.

GUI based clock tree display of launch and capture
After the tree has been balanced for optimal skew and all the paths in bunches have been treated with utmost care, still some work needs to be done. Finer details of clock path for each timing path need to be examined. For this, the clock path for launch and capture may be extracted and compared in a gui such as tkdiff or vi in diff mode. Similar analysis may be performed in timing reports produced by EDI tool, but as these reports report launch and capture path in succession, it is cumbersome to compare the launch and capture paths. Extracting the launch and capture clock paths and analysing in GUI brings ease of analysis as launch and capture path are displayed in parallel. Also, we can analyse what all cells are there in launch and capture paths, how much path is common, whether the cells used are of appropriate type etc. Also, we may play with scripting to include what all case settings are there in the clock path, what all cells are there etc. We present below an example of the output generated by the procedure we developed for the same.

Shown on left is the path traced by launch clock and on right is the path traced by capture clock. We have chosen to extract the arrival times, fanout, arcs and constant values for the clock path. Library cell for the clock cells in the launch and capture path can also be chosen to be shown along with these. The simple procedure that we followed to generate above report is as shown in figure 4.

Figure 4: Extracting launch and capture paths to show in GUI.

So these are few of the techniques we developed for post-CTS design cycle. All these algorithms are implementable with vendor command tool sets. These analysis/debugging procedures are helpful in enabling faster timing/implementation closure cycles.

About the authors
Vijay Bhargava is Lead Design Engineer at Freescale Semiconductors, Noida. In his career spanning 11 years, Vijay Bhargava has worked extensively on verification, digital IP, power estimation/modelling and DSP architectures. He has handled synthesis/APR and STA activities for SoC physical design.

Gourav Kapoor is Design Engineer at Freescale Semiconductors, Noida. He has been holding the said position for two years. He is part of the physical design team and responsible for constraints development and timing closure. He has been involved in both chip-level and block-level timing closure for various SoCs at 65nm and 45nm.

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