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Pre-CTS clock path timing analysis, automation

Posted: 08 May 2013     Print Version  Bookmark and Share

Keywords:VLSI  timing closure  clock tree synthesis 

SoC very-large-scale integration (VLSI) design flow involves two major steps: frontend and backend. While frontend involves design coding and verification of the design intent, backend is where the physical implementation of the logic takes place. Physical design takes the design through various sub-steps (synthesis, placement, routing, signal-integrity etc.) with the goal of implementing the design with minimal area and optimum timing performance. It has been observed that managing clock paths and their timing is one of the most challenging tasks in physical design flow which, if properly taken care of, would ease and help faster timing closure cycles. On the contrary, failure in handling the clock tree properly brings many challenges to timing closure process later in the design flow.

In this article, we present a couple of techniques that can be pretty useful in early, or pre-clock tree synthesis (CTS), stages of physical design to help the designers efficiently utilise the time and minimise the effort. Every technique below would have a general description and a typically formatted report for the same. After which we would have the algorithm/procedure we deployed to achieve the report explained. Post-CTS clock path timing analysis will be dealt with in Part 2 of this series.

Figure 1: An example primitive clocking structure.

Clock architecture in the initial stages of the design
Exploration and understanding of the clock architecture and clocking structure is the first step towards timing constraint development. By clocking structure we mean the root clock sources, clock path, clock dividers (generated clock sources), clock control signals etc. So for architectural understanding we essentially need to know all the potential clock sources (root or generated) and the modules being driven by them. This helps in defining clocks in accordance with the clocking architecture (Frequencies, synchronous and asynchronous clock relationships and waveforms). Typical root clock sources in an SoC would be on-chip PLLs and oscillators and external off-chip clock sources. Similarly generated clock sources usually are clock dividers involving flops, multiplexers or clock gating cells. Preliminary information regarding root sources can be easily taken from the design architecture document. These would then be passed on to some kind of procedure which would report the clock fanout in properly formatted structure. Most EDI tools have a GUI interface to trace the clocking structure, but using that to trace entire clock path is quite cumbersome and time consuming. So, it is important to have a faster approach. We present below one way of reporting the clocking structure in textual format (reported by the procedure we developed). While reporting, we may ignore the clock buffers/other combinational gates in the path as they introduce complexity in reporting and are less significant in terms of understanding of clocking structure. Very often, is is sufficient only to have knowledge of clock gating cells/dividers in the clock path and what all hierarchies are driven through these.


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