Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Embedded

Enable peaceful coexistence of MicroBlaze, Zynq

Posted: 08 Apr 2013     Print Version  Bookmark and Share

Keywords:SoC  programmable logic  PCIe  RAM 

The Xilinx Zynq-7000 All Programmable SoC already has plenty of processing power onboard. However, the presence of powerful twin Cortex-A9 processors and associated peripherals in Zynq's application processing unit (APU) should not keep you from adding one or more MicroBlaze processors in the same package, if your application would benefit from them.

Why might you want to add a MicroBlaze to a solution already endowed with serious processing clout? First there is the issue of reliability. Single-threading dramatically improves reliability. You can cleanly place one thread per Cortex-A9 (for computationally intensive tasks), and instantiate as many MicroBlaze processors as you need for other threads. Second, you can farm out any housekeeping chores that don't require the power of a Cortex-A9 to a MicroBlaze, thus saving critical performance cycles for the jobs that need them most.

Here's an example that covers both of the above situations. Consider a task that requires long stretches of intense computing while monitoring user input. Here the MicroBlaze could manage the user input (lower frequency, non-computationally intensive) and write into the APU's memory space so that when the APU "comes up for air" – that is, completes its processing task – It can see what information it needs to process next.

Once you've made the decision to include a MicroBlaze processor in your Zynq-based design, several issues become immediately apparent. First and foremost is the question of how the APU will communicate with the MicroBlaze, and what processing system (PS) resources are available for the MicroBlaze. Many boards, such as the ZC702 and Zedboard, map many of the peripherals directly to the pins connected to the PS. These pins are not directly accessible to the MicroBlaze in the programmable logic (PL). The PS also contains a variety of timers and interrupt sources. Is there any way to access them from the domain of the MicroBlaze?

Figure 1: Is the boundary between the PS and the MicroBlaze within the PL a minefield, or can the two share resources?

Interfaces between the PS and PL
The processor system and the programmable logic are well coupled. This means that there are multiple tightly integrated connections be¬tween the Cortex-A9s, snoop control unit (SCU), PS peripherals, clock management and other functions, and the programmable logic. In fact, there are six different types of interconnects between the PS and the PL, and you can use them in conjunction with one another. Additionally, many of these paths are symmetric—that is, the PS can initiate or "master" connections to the PL and the PL can master connections to the PS.

Much of the information presently available from Xilinx, from app notes to user guides and white papers, illustrates how the Zynq-7000 APU, as the "centre" of the design, can use the programmable logic to access memory, PL-based peripherals and hard silicon peripherals such as the PCIe block, Block RAMs, DSP48s and multi-gigabit transceivers. In examining how the MicroBlaze can be the captain of its domain, the logical place to begin is by looking at the six interface varieties, starting with three types of AXI interfaces: general purpose, high performance and the Accelerator Coherency Port.

The PS is equipped with two master AXI channels to the PL and two slave channels mastered by the PL (figure 2). "Master" in this context means that the AXI channel is the initiator and can begin data exchanges, whereas a "slave" can only respond to arriving data. The master AXI channels are typically used to communicate with peripherals located in the PL. The slave AXI channels respond to requests made from the PL, which can include transactions made by MicroBlaze processors. These AXI channels tie into the central interconnect of the PS and can be routed to many resources.

Figure 2: Simplified connections to the processing system's central interconnect.

1 • 2 • 3 • 4 Next Page Last Page

Comment on "Enable peaceful coexistence of Micro..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top