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Consortium studies stress on CU interconnects

Posted: 28 Mar 2013     Print Version  Bookmark and Share

Keywords:copper wire bonding  semiconductor devices  interconnects 

The Copper (Cu) Wire Bonding Consortium started by the Institute of Microelectronics (IME) commences its second phase that will focus on tackling copper wire bonding issues related to corrosion and stress for improved reliability of semiconductor devices.

Copper, which offers favourable cost, performance, quality and reliability benefits over gold, has become one of the preferred materials for wire bonding interconnects in microelectronics. Today, however, the industry still faces many technical challenges in developing copper as the best choice for chip-to-package interconnection.

One of the key technical issues is related to copper's hardness relative to gold, which requires bonding parameters to be very well controlled in order to eliminate the risk of damaging bond pads and underlying structures. Another daunting challenge of using copper is its reactivity with oxygen in the surrounding air which causes corrosion-related problems.

To understand the effects of copper wire hardness when bonding on different materials, the consortium will carry out modelling and characterisation of copper wire bonding stress using stress sensors developed under the scope of Phase I of the Cu Wire Consortium to provide an improved technique of measuring wire bonding stress. The outcome of this work will enable semiconductor manufacturers as well as test and packaging houses to develop solutions to improve product reliability, especially those targeted at high reliability applications.

Phase I was launched in 2010 with companies Atotech, Globalfoundries, Heraeus Materials and Infineon Technologies signing up as key members.

"Globalfoundries is pleased to be in this consortium as the first phase of our partnership has successfully resulted in optimising 0.7 mil in copper wire bonding on our 40nm product and passed the JEDEC reliability test. The success has brought us to the next phase of collaboration where the process will be tested on our advanced 28nm product," said Globalfoundries Singapore SVP and GM K. C. Ang.

"The consortium members are of various backgrounds, such as wafer manufacturers, mould compound manufacturers and end users. The wafer manufacturers design pad structures that cater for the harder copper wire which created challenges on 1st bond mechanical stress during bonding and package reliability due to corrosion. Other partners are mould compound manufacturers and end users who can equally contribute to materials and assessment on best combination of package design, materials and application solution," commented Heraeus Matertials EVP Bernd Stenger.

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