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An overview of offloading CPUs to FPGAs

Posted: 18 Mar 2013     Print Version  Bookmark and Share

Keywords:High Performance Reconfigurable Computing  C algorithms  C-to-HDL compiler 

Some students decided to implement PNG in naive way using algorithms called trial division; that is, by checking if a number can be divided, without a remainder, only by itself. As a "reward," they had to implement some "nasty" operation in VHDL, like a modulus or a square root. Many students decided to use the Sieve of Eratosthenes; a few students decided to use the "Fermat's 4k+1" and "Euler's 6k+1" algorithms to check if a number is a prime. The best method was one proposed by student Grzegorz Glowka BSc due to its adaptation of all three previously mentioned algorithms. Student Glowka observed that—in some intervals—some methods are more efficient than others, and he implemented his PNG in such a manner as to leverage this fact.

The lessons from the exercise were as follows:

 • Implement everything in C and perform software simulations, then run working applications and tests that measure their performance in the hardware
 • Find weaknesses of C-to-HDL translation and eliminate them by replacing them with regards to HDL blocks. Regenerate the whole design, implement it in hardware, and then run tests and measure their performance.
 • Consider rewriting key elements in HDL to tune performance.
 • Rewrite the whole hardware part into HDL, or only those parts that are responsible for data processing, leaving C to interface and transmit data, etc.

Since we are teachers, our students are our "results." We are happy to report that both their grades were up (from prior years of similar coursework) and that students felt a little more prepared for corporate life. The class continues to develop. If we get positive responses from this article, we will share more of the teaching units. Also, please feel free to contact the authors to share or exchange teaching materials.

The authors would like to acknowledge the assistance given by Brian Durwood of Impulse Accelerated Technologies in the preparation of this article.

About the authors
Grzegorz Gancarczyk was born in Nowy Sacz, Poland, in 1984. He received an MSc degree in the field of electronics from the AGH University of Science and Technology (AGH-UST), Krakow, Poland, in 2009.

Since 2009, he is with the Academic Computer Centre (ACC) CYFRONET AGH, Krakow, Poland and now also with the Department of Electronics, AGH-UST, Krakow, Poland. His research interests include engineering education, statistics, stochastic processes, phenomenon of noise, digital signal processing and hardware acceleration of numerical methods.

Maciej Wielgosz was born in Krakow, Poland, in 1979. He received his MSc and PhD degrees in the field of electronics from the AGH-UST, Krakow, Poland, in 2005 and 2010, respectively.

Since 2005, he is with the ACC CYFRONET AGH, Krakow, Poland and since 2009 also with the Dept. of Electr., AGH-UST, Krakow, Poland. He has published over 40 papers in journals and conferences and also one book: "FPGA implementation of the selected floating point operations" (Warszawa: Akademicka Oficyna Wydawnicza EXIT, 2010). His research interests include educational issues in electronics, data compression, neural networks and hardware acceleration of computations.

Kazimierz Wiatr was born in Tarnow, Poland, in 1955. He received MSc and PhD degrees in the field of electrical engineering from the AGH-UST, Krakow, Poland, in 1980 and 1987, respectively, D. Hab. (habilitation) degree in electronics from the University of Technology of Lodz, Lodz, Poland, in 1999. Professor degree in 2002.

Since 1980, he works at the Dept. of Electr., AGH-UST, Krakow, Poland. Head of Reconfigurable Computing Systems Group. Since 2004 director of the ACC CYFRONET AGH. Since 2006 chairman of the board of PIONIER—Polish Optical Internet—Consortium. Between 1998 and 2002 adviser to the Prime Minister of Poland on "educational and upbringing of the young generation". Managed 9 Polish Scientific Research Committee research grants. His works resulted in over 200 publications, 19 books, 5 patents and 35 industrial implementations. Achieved Polish Science and Higher Education Minister's Award. Has been involved with youth education for more than 30 years. One of the founders of the Polish independent scouting movement. His research interests include educational issues, processes automation, image systems, multi-processor and many core systems, reconfigurable devices and hardware methods of calculations accelerating.

Prof. Wiatr was appointed in 2007 to a chairman of Tarnow Scientific Society. Member of the Polish Information Processing Society, European Organization for Information and Microelectronics (EUROMICRO). In the Sixth and Seventh Term Senate was a chairman of the Science, Educational and Sport Committee. Reviewer in the IEEE Expert Magazine, IEE Computer and Digital Techniques, IEE Electronic Letters, IEEE Transactions on Neural Networks, Eurasip Journal on Applied Signal Processing, Journal Machine Graphics and Vision.

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