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Guide to early power analysis

Posted: 27 Feb 2013     Print Version  Bookmark and Share

Keywords:system-on-a-chip  register transfer level  simulation 

Many designs these days are derivative designs using the same technology node and libraries. In these cases, parts of the design have already gone through back-end place and route. So when we create a new design using exiting blocks, the early power analysis flow should be able to capture characteristics like capacitance, cell distribution, VT-mix, clock tree buffers, etc. It is important to support a completely automated flow of scavenging the key attributes from the netlist and apply them in RTL power estimation. At the same time, the flow should provide the flexibility for an advanced user to fine-tune the scavenged data.

Figure 2: Scavenging existing technology netlist for accurate RTL power analysis.

The following factors affect components of power in the early analysis flow and relevant useful data can be brought into the RTL power estimation for new designs based on an existing netlist with the same technology nodes and libraries:

 • The synthesis engine should be fast enough but relatively accurate to match the area characteristics of actual implementation tools. Synthesis will have to use scan cells, as the final power correlation is being done with scanned netlist design.
 • In general, power analysis tools use minimum area-based cell mapping and may use cells that have very low drive strengths, and therefore this may result in power discrepancies. To work around this problem, use "don't_use" or "don't_touch" synthesis constraints on cells that have low drive strengths.
 • The power analysis tool needs to account for the impact of clock buffers added to clock trees and other buffers added to high-fanout nets.
 • In a few cases, libraries might have multiple power rails or blocks in the design that are in switched off power domains. In some cases, you may have different libraries that are operating at different voltages.
 • Clock power depends on the way clock gating is done in the design. By default, clock gating is not done in an early power analysis tool and the flow needs to infer an existing clock gating threshold.

Guideline 3: Do early physically-aware power estimation for timing sensitive designs
In advanced technology nodes, it is common that the overall power at RTL correlates well with the final netlist power. However, the individual sub-components of leakage power, internal power or combinational power do not match that of the final design. This is an inherent drawback of area-based synthesis for early power estimation and hence requires a solution that considers physical and timing constraints early at RTL to get more accurate results for power.

It is also important for the power analysis tool to read in the timing constraints in Synopsys Design Constraints (SDC) format to improve the power estimation results. The tool should also be able to take in physical libraries and do timing optimisation and the changes for fixing design rule violations along with the slew calculation. The flow should also support the use of different versions of libraries (like nominal for power and worst for timing) for timing optimisation and power computation. Further, with smaller geometries, the interconnect capacitance is becoming more significant. Thus many libraries do not have wire load models. In the absence wire load models, a flow that has a quick prototyping placement and floor plan module can extract fairly acute wiring capacitances.

Timing and physical optimisation steps are time consuming and the tool needs to trade-off fast run times at RTL and accuracy in power estimation.

Figure 3: Early physically-aware power analysis.

Guideline 4: Perform early RTL scan power estimation
SoC designs have multiple scan chains; each of them may have several thousand flops. If all the chains are run at the same time, then power dissipation is too high. Hence scan power is a key factor for deciding chip packaging. The power grid is designed with a certain maximum power, based on normal operational mode. If the power during test mode is significantly more, it may be necessary to slow down scan patterns or test certain blocks only. Both of these methods can cause excess cost due to higher test time.

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