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Reduce tester-based silicon debug time (Part 2)

Posted: 25 Jan 2013     Print Version  Bookmark and Share

Keywords:verification for test stage  debugging  SoC 

Make sure the freezing of the main clock (for example, before taking system to reset) and restarting (once we are out of reset) of the main clock on which the VCD is based are done following these guidelines: in exact multiples of the cycle period, never on a half clock period , (i.e., the time from the positive edge of clock before freezing), and on the positive edge of clock on restarting using an integral multiple of the clock period. This latter maintains cycle synchronisation which aids smother operation on tester (since cycle based nature needs to be maintained).

To finish off the testcase execution in a synchronised manner, in case the pattern expects some return value (to signal pass/fail) from the core side code sent out on the same pads as those used for downloading the code, probed by the verilog component. Then this probing needs to be enabled only after the download has finished since otherwise random code-data being downloaded can trigger off a false pass/fail and lead to a testcase finish before actual code execution even starts.

Test mode entry schemes and their start-up and shutdown sequences must be developed such that the VCDs are compliant for running back-to-back on tester. Doing this will enable faster execution on the tester by trimming the start and end of the VCDs and joining them end-to-end, running one after the other, without needing a power-off/on in between.

If the design is such that the peripheral clocks are disabled by default during and after power-up, then for each test-case you should start with a clock enabling macro to enable the clock of each module. Otherwise, the pattern may get stuck while accessing register of modules whose clocks are not even enabled.

VCD should not have any internal signal forcing/probing or any hard delays.

As far as possible, the cache should not be enabled by default since it can cause unpredictable failures, making debugging difficult.

As far as possible and as allowed by memory constraints, hex patterns should always be loaded into the backup-system RAM (which is active even in low-power modes) so that all patterns can be tuned to run into low-power modes if required.

The source code for the tester should be highly optimised to reduce memory and time during download.

The pads being used to signal some output on tester should always have their slew rates programmed to values that ensure their fastest behaviour. Otherwise you may end up in a loop, debugging some unnecessary slow pad issue.

For a signature on Tester cases, no pad should be toggling at the frequency of the input clock of the pattern. In other words , the input clock should be the fastest clock in the VCD (apart from the PLL /DDR output clocks) to ensure proper sampling of all transitions.

INFO/DEBUG statements should never be used in the Tester patterns. Their use unnecessarily increases the code length. Their use also leads to porthole issues. Not only does this put a strain on the already limited memory on the tester and lead to unnecessary debug ( such as in case the porthole locations), the scheme doesn't work reliably when implemented in silicon.

These best practice recommendations are the result of insights gained by generating the VFT testbench infrastructure, creating and simulating the tester patterns, and debugging the failures observed in simulation as well as on silicon.

Through the use of such "learning from experience" procedures in new projects we have saved unnecessary iterations of simulation pass/silicon failure pattern/infrastructure modification for most of the patterns. Instead, they are caught early on in simulation itself and result in the delivery of pattern VCDs which are correct by construction.

This has also reduced functional tester pattern bring-up time, as well as tester time and debug effort. This combination ultimately brings down the overall cost of chip design and test but at the same time results in higher quality performance at customer end. We consider these techniques generic and capable of ensuring an improvement in overall efficiency of VFT engineers.

About the authors
Neha Srivastava is a lead design engineer at Freescale Semiconductors (Noida, India Design Centre),ÿworking in the Automotive and Industrial Solution Group (AISG) for over 5 years. She has a Bachelor of Engineering (B.E.) degree from Birla Institute of Technology and hasÿworked on multiple SoCs in front-end verification and Verification for Testing domain, with areas of interest being low power designs, safety architectures, and high performance systems.

Aashish Mittal is a principle design engineer at Freescale Semiconductors (Noida, India Design Centre), working in the Automotive and Industrial Solution Group(AISG) for over 12 years. He has a Master of Technology from Banaras Hindu University and has worked on multiple SoCs in front-end verification, Testbench Integration and Verification for Testing domain, with areas of interest being dual core, security, debug, and low power architecture.

Nitin Goel is senior design engineer at Freescale Semiconductor India Pvt. Ltd, working in the Automotive Microcontroller Group (AMCG) for over 6 years . He graduated from Netaji Subhash Institute Of Technology, Delhi in 2006. Since then he has been working in frontend verification domain. Along with an experience in IP Level , SoC Level, and Core verification , he has been working in Tester pattern development and debugging.

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